EEWORLDEEWORLDEEWORLD

Part Number

Search

LT1568CGN#TR

Description
IC block build fltr lonos 16ssop
CategoryAnalog mixed-signal IC    filter   
File Size270KB,16 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Download Datasheet Parametric Compare View All

LT1568CGN#TR Overview

IC block build fltr lonos 16ssop

LT1568CGN#TR Parametric

Parameter NameAttribute value
Brand NameLinear Technology
Is it Rohs certified?incompatible
MakerLinear ( ADI )
Parts packaging codeSSOP
package instructionSSOP,
Contacts16
Manufacturer packaging codeGN
Reach Compliance Code_compli
ECCN codeEAR99
Active filter typeCONTINUOUS TIME FILTER
Other featuresSINGLE 4-POLE OR MATCHED PAIR OF 2-POLE LOWPASS FILTERS; CAN OPERATE FROM SINGLE 5V OR 3V NOM SUPPLY
Center frequency or cutoff frequency maximum range10000 kHz
Center frequency or cutoff frequency minimum range200 kHz
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length4.8895 mm
Humidity sensitivity level1
Maximum negative supply voltage (Vsup)-5.5 V
Negative supply voltage minimum (Vsup)-1.35 V
Nominal Negative Supply Voltage (Vsup)-5 V
Number of functions2
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)255
poles and zeros2 AND 0
Certification statusNot Qualified
responseLOWPASS/BANDPASS
Maximum seat height1.727 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.35 V
Nominal supply voltage (Vsup)5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
transfer characteristicsBUTTERWORTH/BESSEL/CHEBYSHEV
width3.9 mm
FEATURES
s
s
LT1568
Very Low Noise,
High Frequency Active RC,
Filter Building Block
DESCRIPTIO
The LT
®
1568 is an easy-to-use, active-RC filter building
block with rail-to-rail inputs and outputs. The internal ca-
pacitors of the IC and the GBW product of the internal low
noise op amps are trimmed such that consistent and repeat-
able filter responses can be achieved. With a single resis-
tor value, the LT1568 provides a pair of
matched
2-pole
Butterworth lowpass filters with unity gain suitable for I/Q
channels.
By using unequal-valued external resistors, the two 2-pole
sections can create different frequency responses or
gains. In addition, the two stages may be cascaded to
create a single 4-pole filter with a programmable re-
sponse. Capable of cutoff frequencies up to 10MHz, the
LT1568 is ideal for antialiasing or channel filtering in high
speed data communications systems. The LT1568 can
also be used as a bandpass filter.
The LT1568 features very low noise, supporting signal-to-
noise ratios of over 90dB. It also provides single-ended to
differential signal conversion for directly driving high
speed A/D converters. The LT1568 has a shutdown mode
that reduces supply current to approximately 0.5mA on a
5V supply.
The LT1568 is available in a narrow 16-lead SSOP
package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
s
s
s
s
s
s
s
s
Up to 10MHz Center Frequency on a Single 3V
Supply
Easy to Use—A Single Resistor Value Sets Lowpass
Cutoff Frequency (200kHz
≤ ƒ
C
5MHz), Unequal
Resistor Values Extend Cutoff Frequency Up to
10MHz
Extremely Flexible—Different Resistor Values
Allow Lowpass Transfer Functions with or Without
Gain (Butterworth, Chebyshev or Custom)
SNR = 92dB (ƒ
C
= 2MHz, 2V
P-P
)
THD = –84dB (ƒ
C
= 2MHz, 1V
P-P
)
Internal Capacitors Trimmed to
±0.75%
Single 4-Pole Lowpass Filter or
Matched Pair
of
2-Pole Lowpass Filters
Can be Connected as a Bandpass Filter
Single-Ended or Differential Output
Operates from Single 3V (2.7V Min) to
±5V
Supply
Rail-to-Rail Input and Output Voltages
APPLICATIO S
s
s
s
s
s
Replaces Discrete RC Active Filters and LC Filter
Modules
Antialiasing/Reconstruction Filters
Dual or I-and-Q Channels (Two Matched 2nd Order
Filters in One Package)
Single-Ended to Differential Conversion
Video Signal Processing
TYPICAL APPLICATIO
3V
0.1µF
1
511Ω
V
INA
V
OUTA
V
OUTA
511Ω
511Ω
2
3
4
5
6
0.1µF 7
8
Amplitude and Phase Matched Dual Butterworth 2.5MHz Lowpass
Filter with Differential Output. Single 3V Supply Operation
16
V
+
LT1568
15
INVA
INVB
14
SA
SB
13
OUTA
OUTB
12
OUTA
OUTB
11
GNDA GNDB
10
NC
EN
9
V
V
V
+
Amplitude Response
3
0
–3
511Ω
511Ω
GAIN (dB)
–6
V
INB
V
OUTB
511Ω
V
OUTB
THE PROPRIETARY ARCHITECTURE
ALLOWS FOR A SIMPLE RESISTOR
CALCULATION:
10MHz
R = 128Ω •
;
ƒ
C
= CUTOFF FREQUENCY
ƒ
C
–9
–12
–15
–18
–21
–24
–27
100k
1M
FREQUENCY (Hz)
10M
1568 TA02
1568 TA01
U
U
U
1568f
1

LT1568CGN#TR Related Products

LT1568CGN#TR LT1568CGN#TRPBF LT1568IGN#TRPBF LT1568IGN#PBF
Description IC block build fltr lonos 16ssop IC BLOCK BUILD FLTR LONOS 16SSOP IC BLOCK BUILD FLTR LONOS 16SSOP IC BLOCK BUILD FLTR LONOS 16SSOP
Brand Name Linear Technology Linear Technology Linear Technology Linear Technology
Is it Rohs certified? incompatible conform to conform to conform to
Maker Linear ( ADI ) Linear ( ADI ) Linear ( ADI ) Linear ( ADI )
Parts packaging code SSOP SSOP SSOP SSOP
package instruction SSOP, SSOP, SSOP, SSOP, SSOP16,.25
Contacts 16 16 16 16
Manufacturer packaging code GN GN GN GN
Reach Compliance Code _compli compliant compliant compliant
ECCN code EAR99 EAR99 EAR99 EAR99
Active filter type CONTINUOUS TIME FILTER CONTINUOUS TIME FILTER CONTINUOUS TIME FILTER CONTINUOUS TIME FILTER
Other features SINGLE 4-POLE OR MATCHED PAIR OF 2-POLE LOWPASS FILTERS; CAN OPERATE FROM SINGLE 5V OR 3V NOM SUPPLY SINGLE 4-POLE OR MATCHED PAIR OF 2-POLE LOWPASS FILTERS; CAN OPERATE FROM SINGLE 5V OR 3V NOM SUPPLY SINGLE 4-POLE OR MATCHED PAIR OF 2-POLE LOWPASS FILTERS; CAN OPERATE FROM SINGLE 5V OR 3V NOM SUPPLY SINGLE 4-POLE OR MATCHED PAIR OF 2-POLE LOWPASS FILTERS; CAN OPERATE FROM SINGLE 5V OR 3V NOM SUPPLY
Center frequency or cutoff frequency maximum range 10000 kHz 10000 kHz 10000 kHz 10000 kHz
Center frequency or cutoff frequency minimum range 200 kHz 200 kHz 200 kHz 200 kHz
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e0 e3 e3 e3
length 4.8895 mm 4.8895 mm 4.8895 mm 4.8895 mm
Humidity sensitivity level 1 1 1 1
Maximum negative supply voltage (Vsup) -5.5 V -5.5 V -5.5 V -5.5 V
Negative supply voltage minimum (Vsup) -1.35 V -1.35 V -1.35 V -1.35 V
Nominal Negative Supply Voltage (Vsup) -5 V -5 V -5 V -5 V
Number of functions 2 2 2 2
Number of terminals 16 16 16 16
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP SSOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 255 260 260 260
poles and zeros 2 AND 0 2 AND 0 2 AND 0 2 AND 0
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
response LOWPASS/BANDPASS LOWPASS/BANDPASS LOWPASS/BANDPASS LOWPASS/BANDPASS
Maximum seat height 1.727 mm 1.727 mm 1.727 mm 1.727 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 1.35 V 1.35 V 1.35 V 1.35 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V
surface mount YES YES YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm 0.635 mm 0.635 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 40 30 30 30
transfer characteristics BUTTERWORTH/BESSEL/CHEBYSHEV BUTTERWORTH/BESSEL/CHEBYSHEV BUTTERWORTH/BESSEL/CHEBYSHEV BUTTERWORTH/BESSEL/CHEBYSHEV
width 3.9 mm 3.9 mm 3.9 mm 3.9 mm
Can FPGA realize the digital processing requirements of DSP?
Generally, digital processing and logic control are implemented using DSP plus FPGA. Recently, I want to use FPGA to implement digital processing and logic control. I heard from someone in communicati...
yaking86 FPGA/CPLD
How to achieve wireless interconnection between two machines?
There are two computers, more than 200 meters apart. How can I use a wireless network card to connect the two computers? Is it possible without wireless routing and wireless access?...
wujieflash Embedded System
Help: When debugging the kernel on Marvell PXA310, after the kernel starts, the serial port does not output any startup information. Tip: The serial port cannot be registered. Attached: DEBUG debugging information
I am working on Android porting recently. I patched and compiled the linux kernel provided by Marvell, generated a kernel zImage file, and downloaded it to the pxa310 platform through blob tftp. The c...
qinxuewei101 Embedded System
Clock design based on DS1302 chip
Clock design based on DS1302 chip...
hai88920081 MCU
usart1 problem
Can anyone give me a routine program for using USART1 as asynchronous communication UART? I have been debugging for a long time, but there is still an error.My program is: Can anyone help me find wher...
scliujun stm32/stm8
[EEWORLD University TI Classroom] It would be even better if we added some experiments and solution demonstrations!
First of all, I would like to thank my friends at EEWORLD and the training engineers at TI. I feel that I have gained a lot from listening to this video ! However, I have the following feelings during...
乌合之众 Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2737  836  2294  214  2324  56  17  47  5  43 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号