DS21Q55
Quad T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21Q55 is a quad software-selectable T1, E1,
or J1 MCM device for short-haul and long-haul
applications. Each port is composed of a line
interface unit (LIU), framer, HDLC controllers, and a
TDM backplane interface, and is controlled by an
8-bit parallel port configured for Intel or Motorola
bus operations. The DS21Q55 is software compatible
with the DS2155 single-chip transceiver. It is pin
compatible with the DS21Qx5y family of products.
Each LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line build-outs as well as CSU line build-outs
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75W
coax and 120W twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
FEATURES
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Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping
CMI Coder/Decoder for Optical I/F
Crystal-Less Jitter Attenuator
Fully Independent Transmit and Receive
Functionality
Dual HDLC Controllers
Programmable BERT Generator and Detector
Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75W/100W/120W T1 and E1 Interfaces
Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
DSL Add/Drop Multiplexers
ORDERING INFORMATION
PART
DS21Q55
DS21Q55N
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
256 BGA
(27mm x 27mm)
256 BGA
(27mm x 27mm)
Pin Configurations appear in Section
2.8.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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DS21Q55 Quad T1/E1/J1 Transceiver
TABLE OF CONTENTS
1.
MAIN FEATURES .........................................................................................................................9
1.1 F
UNCTIONAL
D
ESCRIPTION
...................................................................................12
1.2 B
LOCK
D
IAGRAM
.................................................................................................14
2.
PIN FUNCTION DESCRIPTION ..................................................................................................18
2.1.1 Transmit Side.............................................................................................18
2.1.2 Receive Side..............................................................................................21
2.2 P
ARALLEL
C
ONTROL
P
ORT
P
INS
...........................................................................24
2.3 E
XTENDED
S
YSTEM
I
NFORMATION
B
US
.................................................................25
2.4 JTAG T
EST
A
CCESS
P
ORT
P
INS
..........................................................................26
2.5 L
INE
I
NTERFACE
P
INS
..........................................................................................27
2.6 S
UPPLY
P
INS
.......................................................................................................28
2.7 P
INOUT
...............................................................................................................29
2.8 P
ACKAGE
............................................................................................................35
3.
4.
5.
PARALLEL PORT.......................................................................................................................36
3.1 R
EGISTER
M
AP
....................................................................................................36
SPECIAL PER-CHANNEL REGISTER OPERATION .................................................................43
PROGRAMMING MODEL ...........................................................................................................45
5.1 P
OWER
-U
P
S
EQUENCE
........................................................................................46
5.1.1 Master Mode Register ................................................................................46
5.2 I
NTERRUPT
H
ANDLING
.........................................................................................47
5.3 S
TATUS
R
EGISTERS
.............................................................................................47
5.4 I
NFORMATION
R
EGISTERS
....................................................................................48
5.5 I
NTERRUPT
I
NFORMATION
R
EGISTERS
...................................................................48
6.
7.
7.1
7.2
7.3
7.4
8.
CLOCK MAP ...............................................................................................................................49
T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..........................................50
T1 C
ONTROL
R
EGISTERS
.....................................................................................50
T1 T
RANSMIT
T
RANSPARENCY
.............................................................................55
AIS-CI
AND
RAI-CI G
ENERATION AND
D
ETECTION
................................................55
T1 R
ECEIVE
-S
IDE
D
IGITAL
-M
ILLIWATT
C
ODE
G
ENERATION
....................................56
E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS .........................................59
8.1 E1 C
ONTROL
R
EGISTERS
.....................................................................................59
8.2 A
UTOMATIC
A
LARM
G
ENERATION
.........................................................................63
8.3 E1 I
NFORMATION
R
EGISTERS
...............................................................................64
9.
10.
11.
11.1
12.
12.1
COMMON CONTROL AND STATUS REGISTERS ....................................................................66
9.1 T1/E1 S
TATUS
R
EGISTERS
..................................................................................67
I/O PIN CONFIGURATION OPTIONS .........................................................................................73
LOOPBACK CONFIGURATION .................................................................................................75
P
ER
-C
HANNEL
L
OOPBACK
................................................................................77
ERROR COUNT REGISTERS.....................................................................................................79
L
INE
-C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(LCVCR) ..........................................80
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DS21Q55 Quad T1/E1/J1 Transceiver
12.1.1 T1 Operation ..............................................................................................80
12.1.2 E1 Operation..............................................................................................80
12.2 P
ATH
C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(PCVCR) .........................................82
12.2.1 T1 Operation ..............................................................................................82
12.2.2 E1 Operation..............................................................................................82
12.3 F
RAMES
O
UT
-
OF
-S
YNC
C
OUNT
R
EGISTER
(FOSCR).........................................83
12.3.1 T1 Operation ..............................................................................................83
12.3.2 E1 Operation..............................................................................................83
12.4 E-B
IT
C
OUNTER
(EBCR)..................................................................................84
13.
14.
DS0 MONITORING FUNCTION ..................................................................................................85
SIGNALING OPERATION...........................................................................................................87
14.1 R
ECEIVE
S
IGNALING
........................................................................................87
14.1.1 Processor-Based Signaling ........................................................................87
14.1.2 Hardware-Based Receive Signaling ...........................................................88
14.2 T
RANSMIT
S
IGNALING
......................................................................................93
14.2.1 Processor-Based Mode..............................................................................93
14.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode ..................97
14.2.3 Software Signaling Insertion-Enable Registers, T1 Mode...........................99
14.2.4 Hardware-Based Mode ..............................................................................99
15.
15.1
16.
17.
PER-CHANNEL IDLE CODE GENERATION ............................................................................100
I
DLE
-C
ODE
P
ROGRAMMING
E
XAMPLES
...........................................................101
CHANNEL BLOCKING REGISTERS ........................................................................................105
ELASTIC STORES OPERATION..............................................................................................108
17.1 R
ECEIVE
S
IDE
...............................................................................................111
17.1.1 T1 Mode...................................................................................................111
17.1.2 E1 Mode...................................................................................................111
17.2 T
RANSMIT
S
IDE
.............................................................................................111
17.2.1 T1 Mode...................................................................................................112
17.2.2 E1 Mode...................................................................................................112
17.3 E
LASTIC
S
TORES
I
NITIALIZATION
.....................................................................112
17.4 M
INIMUM
D
ELAY
M
ODE
..................................................................................112
18.
19.
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) ................................................113
T1 BIT-ORIENTED CODE (BOC) CONTROLLER ....................................................................114
19.1 T
RANSMIT
BOC .............................................................................................114
19.1.1 Example: Transmit a BOC........................................................................114
19.2 R
ECEIVE
BOC ...............................................................................................114
19.2.1 Example: Receive a BOC.........................................................................114
20.
20.1
20.2
20.3
21.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) .........................117
M
ETHOD
1: H
ARDWARE
S
CHEME
....................................................................117
M
ETHOD
2: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
D
OUBLE
-F
RAME
..............117
M
ETHOD
3: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
CRC4 M
ULTIFRAME
........120
HDLC CONTROLLERS.............................................................................................................130
21.1 B
ASIC
O
PERATION
D
ETAILS
............................................................................130
21.2 HDLC C
ONFIGURATION
.................................................................................130
21.2.1 FIFO Control ............................................................................................134
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DS21Q55 Quad T1/E1/J1 Transceiver
21.3 HDLC M
APPING
............................................................................................135
21.3.1 Receive ....................................................................................................135
21.3.2 Transmit ...................................................................................................137
21.3.3 FIFO Information ......................................................................................142
21.3.4 Receive Packet-Bytes Available ...............................................................142
21.3.5 HDLC FIFOs ............................................................................................143
21.4 R
ECEIVE
HDLC C
ODE
E
XAMPLE
....................................................................144
21.5 L
EGACY
FDL S
UPPORT
(T1 M
ODE
) ................................................................144
21.5.1 Overview ..................................................................................................144
21.5.2 Receive Section .......................................................................................144
21.5.3 Transmit Section ......................................................................................146
21.6 D4/SLC-96 O
PERATION
.................................................................................146
22.
LINE INTERFACE UNIT (LIU) ...................................................................................................147
22.1 LIU O
PERATION
.............................................................................................147
22.2 R
ECEIVER
.....................................................................................................147
22.2.1 Receive Level Indicator and Threshold Interrupt ......................................148
22.2.2 Receive G.703 Synchronization Signal (E1 Mode) ...................................148
22.2.3 Monitor Mode ...........................................................................................148
22.3 T
RANSMITTER
................................................................................................149
22.3.1 Transmit Short-Circuit Detector/Limiter ....................................................149
22.3.2 Transmit Open-Circuit Detector................................................................149
22.3.3 Transmit BPV Error Insertion....................................................................149
22.3.4 Transmit G.703 Synchronization Signal (E1 Mode) ..................................149
22.4 MCLK P
RESCALER
........................................................................................150
22.5 J
ITTER
A
TTENUATOR
......................................................................................150
22.6 CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
...........................................................150
22.7 LIU C
ONTROL
R
EGISTERS
..............................................................................151
22.8 R
ECOMMENDED
C
IRCUITS
..............................................................................160
22.9 C
OMPONENT
S
PECIFICATIONS
........................................................................162
23.
24.
24.1
24.2
24.3
24.4
24.5
24.6
25.
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION .......................166
BERT FUNCTION......................................................................................................................173
S
TATUS
.........................................................................................................173
M
APPING
.......................................................................................................173
BERT R
EGISTER
D
ESCRIPTIONS
....................................................................175
BERT R
EPETITIVE
P
ATTERN
S
ET
...................................................................179
BERT B
IT
C
OUNTER
......................................................................................180
BERT E
RROR
C
OUNTER
................................................................................181
PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) ..............................................183
25.1 N
UMBER
-
OF
-E
RRORS
R
EGISTERS
..................................................................185
25.1.1 Number-of-Errors Left Register ................................................................186
26.
26.1
26.2
27.
28.
29.
INTERLEAVED PCM BUS OPERATION (IBO).........................................................................187
C
HANNEL
I
NTERLEAVE
...................................................................................187
F
RAME
I
NTERLEAVE
.......................................................................................187
EXTENDED SYSTEM INFORMATION BUS (ESIB)..................................................................190
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER .....................................................194
FRACTIONAL T1/E1 SUPPORT ...............................................................................................195
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DS21Q55 Quad T1/E1/J1 Transceiver
30.
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...............................198
30.1 D
ESCRIPTION
................................................................................................198
30.2 I
NSTRUCTION
R
EGISTER
.................................................................................201
SAMPLE/PRELOAD .............................................................................................202
BYPASS ...............................................................................................................202
EXTEST................................................................................................................202
CLAMP .................................................................................................................202
HIGHZ ..................................................................................................................202
IDCODE................................................................................................................202
30.3 T
EST
R
EGISTERS
...........................................................................................203
30.4 B
OUNDARY
S
CAN
R
EGISTER
..........................................................................203
30.5 B
YPASS
R
EGISTER
........................................................................................203
30.6 I
DENTIFICATION
R
EGISTER
.............................................................................203
31.
31.1
31.2
32.
33.
33.1
33.2
33.3
33.4
34.
FUNCTIONAL TIMING DIAGRAMS ..........................................................................................207
T1 M
ODE
......................................................................................................207
E1 M
ODE
......................................................................................................212
OPERATING PARAMETERS....................................................................................................221
AC TIMING PARAMETERS AND DIAGRAMS .........................................................................223
M
ULTIPLEXED
B
US
AC C
HARACTERISTICS
......................................................223
N
ONMULTIPLEXED
B
US
AC C
HARACTERISTICS
................................................226
R
ECEIVE
-S
IDE
AC C
HARACTERISTICS
.............................................................229
T
RANSMIT
AC C
HARACTERISTICS
...................................................................232
PACKAGE INFORMATION.......................................................................................................235
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