ZL50112GAG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> ZL50112GAG

ZL50112GAG: DescriptionIC cesop processor 552pbga; CategoryWireless rf/communication Telecom circuit; File Size803KB，113 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric Compare View All

ZL50112GAG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	ZL50112GAG	-	-	View	Buy Now

ZL50112GAG Overview

IC cesop processor 552pbga

ZL50112GAG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
Parts packaging code	BGA
package instruction	35 X 35 MM, 1.27 MM, PLASTIC, BGA-552
Contacts	552
Reach Compliance Code	unknow
JESD-30 code	S-PBGA-B552
length	35 mm
Number of functions	1
Number of terminals	552
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA552,26X26,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	2.53 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	35 mm

Preview

Download Datasheet

View All

ZL50110/11/12/14

128, 256, 512 and 1024 Channel CESoP

Processors

Data Sheet

Features

General

•

Circuit Emulation Services over Packet (CESoP)

transport for MPLS, IP and Ethernet networks

On chip timing & synchronization recovery across

a packet network

Grooming capability for Nx64 Kbps trunking

Ordering Information

ZL50110GAG

552 PBGA

Trays, Bake

ZL50111GAG

552 PBGA

Trays, Bake

ZL50112GAG

552 PBGA

Trays, Bake

ZL50114GAG

552 PBGA

Trays, Bake

ZL50110GAG2 552 PBGA** Trays, Bake

ZL50111GAG2 552 PBGA** Trays, Bake

ZL50112GAG2 552 PBGA** Trays, Bake

ZL50114GAG2 552 PBGA** Trays, Bake

**Pb Fee Tin Silver/Copper

Drypack

October 2009

Circuit Emulation Services

•

Supports ITU-T Recommendation Y.1413 and

Y.1453

Supports IETF RFC4553 and

RFC5086

Supports MEF8 and MFA 8.0.0

Structured, synchronous

CESoP with clock recovery

Unstructured, asynchronous

CESoP, with integral per stream clock recovery

•

-40°C to +85°C

Dual reference Stratum 4 and 4E DPLL for

synchronous operation

•

Network Interfaces

•

Up to 3 x 100 Mbps MII Fast Ethernet or Dual

Redundant 1000 Mbps GMII/TBI Ethernet

Interfaces

System Interfaces

Flexible 32 bit host CPU interface (Motorola

PowerQUICC

™

compatible)

On-chip packet memory for self-contained

operation, with buffer depths of over 16 ms

Up to 8 Mbytes of off-chip packet memory,

supporting buffer depths of over 128 ms

TDM Interfaces

•

Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports

H.110, H-MVIP, ST-BUS backplanes

Up to 1024 bi-directional 64 Kbps channels

Direct connection to LIUs, framers, backplanes

H.110, H-MVIP, ST-BUS backplanes

Triple 100 Mbps MII Fast Ethernet

32 T1/E1, 8 J2, 2 T3/E3 ports

(L IU , F ra m e r, B a c k p la n e )

T rip le

P acket

In te rfa c e

MAC

(M II, G M II, T B I)

P e r P o rt D C O fo r

C lo c k R e c o v e ry

PW , R TP, U D P,

IP v 4 , IP v 6 , M P L S ,

E C ID , V L A N , U s e r

D e fin e d , O th e rs

O n C h ip P a c k e t M e m o ry

Backplane

(J itte r B u ffe r C o m p e n s a tio n fo r 1 6 -1 2 8 m s o f P a c k e t D e la y V a ria tio n )

Clocks

D u a l R e fe re n c e

D PLL

H o s t P ro c e s s o r

In te rfa c e

E x te rn a l M e m o ry

In te rfa c e (o p tio n a l)

3 2 -b it M o to ro la c o m p a tib le P Q II®

Z B T -S R A M

(0 - 8 M b y te s )

Figure 1 - ZL50111 High Level Overview

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

TBI Gigabit Ethernet

TDM

In te rfa c e

M u lti-P ro to c o l

P acket

P ro c e s s in g

E n g in e

Dual Redudnat 1000 Mbps GMII/

ZL50110/11/12/14

Description

Data Sheet

The ZL50110/11/12/14 family of CESoP processors are highly functional TDM to Packet bridging devices. The

ZL50110/11/12/14 provides both structured and unstructured circuit emulation services over packet (CESoP) for up

to 32 T1, 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also

supports unstructured T3 and E3 streams.

The circuit emulation features in the ZL50110/11/12/14 family supports the ITU Recommendations Y.1413 and

Y.1453, as well as the CESoP standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay

Alliance. The ZL50110/11/14 also supports IETF RFC4553 and RFC5086.

The ZL50110/11/12/14 provides up to triple 100 Mbps MII ports or dual redundant 1000 Mbps GMII/TBI ports.

The ZL50110/11/12/14 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing

the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance

and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery

schemes are included, allowing the customer to choose the correct scheme for the application. An externally

supplied clock may also be used to drive the TDM interface of the ZL50110/11/12/14.

The ZL50110/11/12/14 incur very low latency for the data flow, thereby increasing QoS when carrying voice

services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of

less than 10 ms, does not require expensive processing such as compression and echo cancellation.

The ZL50110/11/12/14 is capable of assembling user-defined packets of TDM traffic from the TDM interface and

transmitting them out the packet interfaces using a variety of protocols. The ZL50110/11/12/14 supports a range of

different packet switched networks, including Ethernet VLANs, IP and MPLS.

The ZL50110/11/12/14 can support up to 4 protocol stacks at the same time, provided that each protocol stack can

be uniquely identified by a mask & match approach.

Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately

queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface.

Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to

maintain timing integrity.

The ZL50110/11/12/14 family includes sufficient on-chip memory that external memory is not required in most

applications. This reduces system costs and simplifies the design. For applications that do require more memory

(e.g., high stream count or high latency), the device supports up to 8 Mbytes of SSRAM.

A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor.

This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI

that runs on a Windows PC.

Zarlink Semiconductor Inc.

ZL50110/11/12/14

Table of Contents

Data Sheet

1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1.1 ZL50111 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1.2 ZL50112 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.3 ZL50110 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1.4 ZL50114 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1.5 TDM Signals Common to ZL50110, ZL50111, ZL50112 and ZL50114 . . . . . . . . . . . . . . . . . . . . . . 31

3.2 PAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.5 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6 System Function Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.7 Test Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.7.1 Administration, Control and Test Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.7.2 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.8 Miscellaneous Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.9 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.10 ZL50111, ZL50112, ZL50110 and ZA50114 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.11 ZL50112 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.12 ZL50112 Auxiliary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.0 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1 Leased Line Provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 Metropolitan Area Network Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.3 Digital Loop Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.4 Remote Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.5 Cell Site Backhaul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.6 Equipment Architecture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3.1 TDM Interface Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3.2 Structured TDM Port Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.3 TDM Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3.3.1 Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3.3.2 Asynchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.4 Payload Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.4.1 Structured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.4.1.1 Structured Payload Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.4.2 Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.6 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.7 Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.8 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.1 Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.3 SYSTEM_CLK Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Zarlink Semiconductor Inc.

ZL50112GAG Related Products

	ZL50112GAG	ZL50110GAG2	ZL50112GAG2	ZL50114GAG	ZL50114GAG2	ZL50110GAG
Description	IC cesop processor 552pbga	IC cesop proc 256ch 552pbga	IC cesop processor 552pbga	IC cesop processor 128ch 552pbga	IC cesop processor 128ch 552pbga	IC cesop processor 256ch 552pbga
Is it Rohs certified?	incompatible	conform to	conform to	incompatible	conform to	incompatible
Maker	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	35 X 35 MM, 1.27 MM, PLASTIC, BGA-552	BGA, BGA552,26X26,50	BGA, BGA552,26X26,50	35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034BAR-2, BGA-552	BGA, BGA552,26X26,50	35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034BAR-2, BGA-552
Contacts	552	552	552	552	552	552
Reach Compliance Code	unknow	compli	compli	unknown	compliant	unknown
JESD-30 code	S-PBGA-B552	S-PBGA-B552	S-PBGA-B552	S-PBGA-B552	S-PBGA-B552	S-PBGA-B552
length	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm
Number of functions	1	1	1	1	1	1
Number of terminals	552	552	552	552	552	552
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA552,26X26,50	BGA552,26X26,50	BGA552,26X26,50	BGA552,26X26,50	BGA552,26X26,50	BGA552,26X26,50
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
power supply	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.53 mm	2.53 mm	2.53 mm	2.53 mm	2.53 mm	2.53 mm
Nominal supply voltage	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm
JESD-609 code	-	-	e1	e0	e1	e0
Terminal surface	-	-	TIN SILVER COPPER	TIN LEAD	TIN SILVER COPPER	TIN LEAD

Recommended Resources

Overview of the new high-voltage DC-DC power module

PCF8591 hardware interface (circuit diagram pin diagram)

OP27 multi-channel S-type thermocouple temperature measurement circuit

Curler power supply circuit using digital control circuit PT8A320P

Three-phase power supply phase sequence dedicated circuit

STK0100 power amplifier circuit

Is there anyone who has an assembly language version of the 51 microcontroller tutorial?: As the title says, I suddenly want to learn assembly language. I feel it is necessary. It doesn't have to be too in-depth, but at least I should have a better understanding of it. Assembly language it...; kobe1941 MCU

Max262 is not flat within the band: After testing, the max262 has a large gain in the band (power supply 5V, input 2V sine wave, there will be a 9V sine wave that is not cut off in the band) and it is not flat. I made three pieces and t...; 一脸大米粥 Electronics Design Contest

Fundamentals of Analog Electronic Circuits--Negative Feedback: [align=left][color=rgb(0, 0, 0)][font=verdana, sans-serif][b][size=4]1. What is feedback? [/size][/b][/font][/color][/align][hr][align=left][color=rgb(0, 0, 0)][font=verdana, sans-serif][size=4]The vo...; Jacktang Analogue and Mixed Signal

Does anyone know what capacitor this is?: Does anyone know what capacitor this is? What does 201GA mean?...; yet Analogue and Mixed Signal

Design of high-speed analog signal chains from DC to broadband: [size=4] The big news in the converter world right now is GSPS ADCs—also known as RF ADCs. With converters on the market sampling at such high rates, the Nyquist frequency has increased 10 times compa...; Jacktang RF/Wirelessly

Design of serial port oscilloscope based on Coreline FPGA development kit: [i=s]This post was last edited by Xiao Meige on 2016-3-26 11:03[/i] [font=Verdana][size=5] [/size][/font][font=Verdana][size=7]All the routines in the attachment are exquisite routines written by Xinh...; 小梅哥 FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components