Features
•
•
•
•
Single Supply for Read and Write: 2.7 to 3.6V
Fast Read Access Time – 55 ns
Internal Program Control and Timer
Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Two Main Memory Blocks (32K Bytes, 64K Bytes)
Fast Erase Cycle Time – 3 Seconds
Byte-by-Byte Programming – 30 µs/Byte Typical
Hardware Data Protection
DATA Polling for End of Program Detection
Low Power Dissipation
– 15 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Green (Pb/Halide-free) Packaging Option
•
•
•
•
•
•
•
1-megabit
(128K x 8)
Single 2.7-volt
Battery-Voltage
Flash Memory
AT49BV001A
AT49BV001AN
AT49BV001AT
AT49BV001ANT
Not Recommended
for New Design
Contact
Atmel to discuss
the latest design in trends
and options
1. Description
The AT49BV001A(N)(T) is a 2.7-volt-only in-system reprogrammable Flash Memory.
Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
55 ns with power dissipation of just 54 mW over the industrial temperature range.
When the device is deselected, the CMOS standby current is less than 50 µA. For the
AT49BV001AN(T), pin 1 for the PLCC package and pin 9 for the TSOP package are
n o c o n n ec t p i ns . T o a l l ow fo r s i m p l e i n - s y s te m r e pr og r a m m ab i l i t y , t h e
AT49BV001A(N)(T) does not require high input voltages for programming. Five-volt-
only commands determine the read and programming operation of the device. Read-
ing data out of the device is similar to reading from an EPROM; it has standard CE,
OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV001A(N)(T)
is performed by erasing a block of data and then programming on a byte by byte
basis. The byte programming time is a fast 30 µs. The end of a program cycle can be
optionally detected by the DATA polling feature. Once the end of a byte program cycle
has been detected, a new access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device inter-
nally controls the erase operations. There are two 8K byte parameter block sections,
two main memory blocks, and one boot block.
The device has the capability to protect the data in the boot block; this feature is
enabled by a command sequence. The 16K-byte boot block section includes a repro-
gramming lock out feature to provide data integrity. The boot sector is designed to
contain user secure code, and when the feature is enabled, the boot sector is pro-
tected from being reprogrammed.
In the AT49BV001AN(T), once the boot block programming lockout feature
is enabled, the contents of the boot block are permanent and cannot be changed.
In the AT49BV001A(T), once the boot block programming lockout feature is enabled,
the contents of the boot block cannot be changed with input voltage levels of 5.5 volts
or less.
3364D–FLASH–3/05
2. Pin Configurations
Pin Name
A0 - A16
CE
OE
WE
RESET
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
RESET
Data Inputs/Outputs
No Connect
2.1
32-lead PLCC Top View
A12
A15
A16
RESET*
VCC
WE
NC
2.2
32-lead VSOP (8 x 14 mm) or 32-lead TSOP, Type 1 (8 x 20 mm) Top View
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
14
15
16
17
18
19
20
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
A11
A9
A8
A13
A14
NC
WE
VCC
*RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Note:
*This pin is a NC on the AT49BV001AN(T).
2
AT49BV001A(N)(T)
3364D–FLASH–3/05
AT49BV001A(N)(T)
3. Block Diagram
AT49BV001A(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
OE
WE
CE
RESET
8
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
1FFFF
X DECODER
MAIN MEMORY
BLOCK 2
(64K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
BOOT BLOCK
(16K BYTES)
10000
0FFFF
PARAMETER
BLOCK 1
(8K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
AT49BV001A(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y-GATING
1FFFF
1C000
1BFFF
CONTROL
LOGIC
Y DECODER
ADDRESS
INPUTS
08000
07FFF
1A000
19FFF
06000
05FFF
18000
17FFF
04000
03FFF
00000
10000
0FFFF
00000
4. Device Operation
4.1
Read
The AT49BV001A(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins is asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
4.2
Command Sequences
When the device is first powered on it will be reset to the read or standby mode depending upon
the state of the control line inputs. In order to perform other device functions, a series of com-
mand sequences are entered into the device. The command sequences are shown in the
“Command Definition Table” on page 6.
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is
latched on the falling edge of CE or WE (except for the sixth cycle of the Sector Erase com-
mand), whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences
are not affected by entering the command sequences.
4.3
Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program or erase operation, the operation
may not be successfully completed and the operation will have to be repeated after a high level
is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device
returns to the read or standby mode, depending upon the state of the control inputs. By applying
a 12V
±
0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if
the boot block lockout feature has been enabled (see
“Boot Block Programming Lockout” on
page 4).
The RESET feature is not available on the AT49BV001AN(T).
3
3364D–FLASH–3/05
4.4
Erasure
Before a byte can be reprogrammed, the main memory blocks or parameter blocks which con-
tains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire
device can be erased at one time by using a 6-byte software code. The software chip erase
code consists of 6-byte load commands to specific address locations with a specific data pattern
(please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase opera-
tion so that no external clocks are required. The maximum time needed to erase the whole chip
is t
EC
. If the boot block lockout feature has been enabled, the data in the boot sector will not be
erased.
4.4.1
Chip Erase
If the boot block lockout has been enabled, the Chip Erase function will erase Parameter
Block 1, Parameter Block 2, Main Memory Block 1 - 2, but not the boot block. If the Boot Block
Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full
chip erase the device will return back to read mode. Any command during chip erase will be
ignored.
4.4.2
Sector Erase
As an alternative to a full chip erase, the device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-
byte parameter block sections and the two main memory blocks can be independently erased
and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector
address is latched on the rising WE edge of the sixth cycle and the 30H data input command is
also latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the
sixth cycle. The erase operation is internally controlled; it will automatically time to completion.
4.5
Byte Programming
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4 bus cycle operation (please refer to the
“Command Definition Table” on page 6).
The
device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs
last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming
is completed after the specified t
BP
cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
4.6
Boot Block Programming Lockout
The device has one designated block that has a programming lockout feature. This feature pre-
vents programming of data in the designated block once the feature has been enabled. The size
of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be activated;
the boot block’s usage as a write protected region is optional to the user. The address range of
the boot block is 00000 to 03FFF for the AT49BV001A(N) while the address range of the boot
block is 1C000 to 1FFFF for the AT49BV001A(N)T.
4
AT49BV001A(N)(T)
3364D–FLASH–3/05
AT49BV001A(N)(T)
Once the feature is enabled, the data in the boot block can no longer be erased or programmed
with input voltage of 5.5V or less. Data in the main memory block can still be changed through
the regular programming method. To activate the lockout feature, a series of six program com-
mands to specific addresses with specific data must be performed. Please refer to the
“Command Definition Table” on page 6.
4.6.1
Boot Block Lockout Detection
A software method is available to determine if programming of the boot block section is locked
out. When the device is in the software product identification mode (see Software Product Iden-
tification Entry and Exit sections) a read from address location 00002H will show if programming
the boot block is locked out for the AT49BV001A(N), and a read from address location 1C002H
will show if programming the boot block is locked out for the AT49BV001A(N)T. If the data on
I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout
feature has been activated and the block cannot be programmed. The software product identifi-
cation code should be used to return to standard operation.
Boot Block Programming Lockout Override
The user can override the boot block programming lockout by taking the RESET pin to 12 volts
during the entire chip erase, sector erase or byte programming operation. When the RESET pin
is brought back to TTL levels the boot block programming lockout feature is again active. This
feature is not available on the AT49BV001AN(T).
4.6.2
4.7
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see
“Operating Modes” on page 7
(for hardware operation) or Software Product
Identification. The manufacturer and device code is the same for both modes.
4.8
DATA Polling
The AT49BV001A(N)(T) features DATA polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been completed, true data is valid on all out-
puts and the next cycle may begin. DATA polling may begin at any time during the program
cycle.
4.9
Toggle Bit
In addition to DATA polling the AT49BV001A(N)(T) provides another method for determining the
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
4.10
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV001A(N)(T) in the follow-
ing ways: (a) V
CC
sense: if V
CC
is below 1.8V (typical), the program function is inhibited. (b)
Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c)
Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program
cycle.
5
3364D–FLASH–3/05
京公网安备 11010802033920号
EEWORLD
