AT45DB081D-SU-2.5-SL383 datasheet, PDF

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AT45DB081D-SU-2.5-SL383: DescriptionIC flash 8mbit 50mhz 8soic; Categorystorage; File Size1MB，53 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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AT45DB081D-SU-2.5-SL383 Overview

IC flash 8mbit 50mhz 8soic

AT45DB081D-SU-2.5-SL383 Parametric

Parameter Name	Attribute value
Datasheets
AT45DB081D
Product Photos
8-SOIC
PCN Obsolescence/ EOL
AT45DB081D Series 10/Sep/2013
Standard Package	2,000
Category	Integrated Circuits (ICs)
Family	Memory
Packaging	Tape & Reel (TR)
Format - Memory	FLASH
Memory Type	DataFLASH
Memory Size	8M (4096 pages x 264 bytes)
Speed	50MHz
Interface	SPI, RapidS
Voltage - Supply	2.5 V ~ 3.6 V
Operating Temperature	-40°C ~ 85°C
Package / Case	8-SOIC (0.209", 5.30mm Width)
Supplier Device Package	8-SOIC

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Features

•

Single 2.5V or 2.7V to 3.6V Supply

•

RapidS Serial Interface: 66MHz Maximum Clock Frequency

•

– SPI Compatible Modes 0 and 3

User Configurable Page Size

– 256-Bytes per Page

– 264-Bytes per Page

– Page Size Can Be Factory Pre-configured for 256-Bytes

Page Program Operation

– Intelligent Programming Operation

– 4,096 Pages (256/264-Bytes/Page) Main Memory

Flexible Erase Options

– Page Erase (256-Bytes)

– Block Erase (2-Kbytes)

– Sector Erase (64-Kbytes)

– Chip Erase (8Mbits)

Two SRAM Data Buffers (256-/264-Bytes)

– Allows Receiving of Data while Reprogramming the Flash Array

Continuous Read Capability through Entire Array

– Ideal for Code Shadowing Applications

Low-power Dissipation

– 7mA Active Read Current Typical

– 25µA Standby Current Typical

– 15µA Deep Power Down Typical

Hardware and Software Data Protection Features

– Individual Sector

Sector Lockdown for Secure Code and Data Storage

– Individual Sector

Security: 128-byte Security Register

– 64-byte User Programmable Space

– Unique 64-byte Device Identifier

JEDEC Standard Manufacturer and Device ID Read

100,000 Program/Erase Cycles Per Page Minimum

Data Retention – 20 Years

Industrial Temperature Range

Green (Pb/Halide-free/RoHS Compliant) Packaging Options

•

8-megabit

2.5V or 2.7V

DataFlash

AT45DB081D

(Not Recommmended

for New Designs)

•

1. Description

The Adesto

AT45DB081D is a 2.5V or 2.7V, serial-interface Flash memory

ideally suited for a wide variety of digital voice-, image-, program code- and data-stor-

age applications. The AT45DB081D supports RapidS

™

serial interface for

applications requiring very high speed operations. RapidS serial interface is SPI com-

patible for frequencies up to 66MHz. Its 8,650,752-bits of memory are organized as

4,096 pages of 256-bytes or 264-bytes each. In addition to the main memory, the

AT45DB081D also contains two SRAM buffers of 256-/264-bytes each. The buffers

allow the receiving of data while a page in the main Memory is being reprogrammed,

as well as writing a continuous data stream. EEPROM emulation (bit or byte alterabil-

ity) is easily handled with a self-contained three step read-modify-write operation.

Unlike conventional Flash memories that are accessed randomly with multiple

3596P–DFLASH–2/2014

AT45DB081D

Table 2-1.

Symbol

Pin Configurations

Name and Function

Chip Select:

Asserting the CS pin selects the device. When the CS pin is deasserted, the device

will be deselected and normally be placed in the standby mode (not Deep Power-Down mode),

and the output pin (SO) will be in a high-impedance state. When the device is deselected, data

will not be accepted on the input pin (SI).

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such as

a program or erase cycle, the device will not enter the standby mode until the completion of the

operation.

Serial Clock:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always

latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the

falling edge of SCK.

Serial Input:

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched on the rising

edge of SCK.

Serial Output:

The SO pin is used to shift data out from the device. Data on the SO pin is always

clocked out on the falling edge of SCK.

Write Protect:

When the WP pin is asserted, all sectors specified for protection by the Sector

Protection Register will be protected against program and erase operations regardless of

whether the Enable Sector Protection command has been issued or not. The WP pin functions

independently of the software controlled protection method. After the WP pin goes low, the

content of the Sector Protection Register cannot be modified.

If a program or erase command is issued to the device while the WP pin is asserted, the device

will simply ignore the command and perform no operation. The device will return to the idle state

once the CS pin has been deasserted. The Enable Sector Protection command and Sector

Lockdown command, however, will be recognized by the device when the WP pin is asserted.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will

not be used. However, it is recommended that the WP pin also be externally connected to V

whenever possible.

Reset:

A low state on the reset pin (RESET) will terminate the operation in progress and reset

the internal state machine to an idle state. The device will remain in the reset condition as long as

a low level is present on the RESET pin. Normal operation can resume once the RESET pin is

brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the

RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended

that the RESET pin be driven high externally.

Device Power Supply:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

Ground:

The ground reference for the power supply. GND should be connected to the system

ground.

Asserted

State

Type

Low

Input

SCK

–

Input

–

Input

Output

Low

Input

RESET

Low

Input

GND

–

Power

Ground

3596P–DFLASH–2/2014

AT45DB081D

5. Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions

and their associated opcodes are contained in

Table 15-1 on page 27

through

Table 15-7 on

page 30.

A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit

opcode and the desired buffer or main memory address location. While the CS pin is low, tog-

gling the SCK pin controls the loading of the opcode and the desired buffer or main memory

address location through the SI (serial input) pin. All instructions, addresses, and data are trans-

ferred with the most significant bit (MSB) first.

Buffer addressing for the DataFlash standard page size (264-bytes) is referenced in the data-

sheet using the terminology BFA8 - BFA0 to denote the nine address bits required to designate

a byte address within a buffer. Main memory addressing is referenced using the terminology

PA11 - PA0 and BA8 - BA0, where PA11 - PA0 denotes the 12 address bits required to desig-

nate a page address and BA8 - BA0 denotes the nine address bits required to designate a byte

address within the page.

For “Power of 2” binary page size (256-bytes) the Buffer addressing is referenced in the data-

sheet using the conventional terminology BFA7 - BFA0 to denote the eight address bits required

to designate a byte address within a buffer. Main memory addressing is referenced using the

terminology A19 - A0, where A19 - A8 denotes the 12 address bits required to designate a page

address and A7 - A0 denotes the eight address bits required to designate a byte address within

a page.

6. Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either

one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and

Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for

details on the clock cycle sequences for each mode.

6.1

Continuous Array Read (Legacy Command: E8H): Up to 66MHz

By supplying an initial starting address for the main memory array, the Continuous Array Read

command can be utilized to sequentially read a continuous stream of data from the device by

simply providing a clock signal; no additional addressing information or control signals need to

be provided. The DataFlash incorporates an internal address counter that will automatically

increment on every clock cycle, allowing one continuous read operation without the need of

additional address sequences. To perform a continuous read from the DataFlash standard page

size (264-bytes), an opcode of E8H must be clocked into the device followed by three address

bytes (which comprise the 24-bit page and byte address sequence) and four don’t care bytes.

The first 12 bits (PA11 - PA0) of the 21-bit address sequence specify which page of the main

memory array to read, and the last nine bits (BA8 - BA0) of the 21-bit address sequence specify

the starting byte address within the page. To perform a continuous read from the binary page

size (256-bytes), the opcode (E8H) must be clocked into the device followed by three address

bytes and four don’t care bytes. The first 12 bits (A19 - A8) of the 20-bits sequence specify which

page of the main memory array to read, and the last eight bits (A7 - A0) of the 20-bits address

sequence specify the starting byte address within the page. The don’t care bytes that follow the

address bytes are needed to initialize the read operation. Following the don’t care bytes, addi-

tional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care

bytes, and the reading of data. When the end of a page in main memory is reached during a

3596P–DFLASH–2/2014

AT45DB081D-SU-2.5-SL383 Related Products

	AT45DB081D-SU-2.5-SL383	AT45DB081D-SSU-2.5	AT45DB081D-SU-2.5	AT45DB081D-SSU-2.5-SL383	AT45DB081D-SU-SL383-AD	AT45DB081D-SSU SL383-AD	AT45DB081D-SU SL955-AD
Description	IC flash 8mbit 50mhz 8soic	IC flash 8mbit 50mhz 8soic	IC flash 8mbit 50mhz 8soic	IC flash 8mbit 50mhz 8soic	IC FLASH 8M SPI 66MHZ 8SOIC	IC FLASH 8M SPI 66MHZ 8SOIC	IC FLASH 8M SPI 66MHZ 8SOIC
technology	-	CMOS	CMOS	-	FLASH	FLASH	FLASH

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