19-6294; Rev 6/12
DS1210
Nonvolatile Controller Chip
FEATURES
Converts CMOS RAMs into Nonvolatile
Memories
Unconditionally Write Protects when V
CC
is
Out-of-Tolerance
Automatically Switches to Battery when
Power-Fail Occurs
Space-Saving 8-Pin PDIP or 16-Pin SO
Packages
Consumes <100nA of Battery Current
Tests Battery Condition on Power up
Provides for Redundant Batteries
Optional 5% or 10% Power-Fail Detection
Low Forward Voltage Drop on the V
CC
Switch
Optional Industrial (N) Temperature Range of
-40°C to +85°C
PIN ASSIGNMENT
VCCO
VBAT1
TOL
GND
1
2
3
4
8
7
6
5
VCCI
VBAT2
CEO
CE
DS1210 8-pin PDIP (300 mils)
NC
VCCO
NC
VBAT1
NC
TOL
NC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
VCCI
NC
VBAT2
NC
CEO
NC
CE
DS1210S 16-pin SO (300 mils)
PIN DESCRIPTION
V
CCO
V
BAT1
TOL
GND
CE
CEO
V
BAT2
V
CCI
NC
- RAM Supply
- + Battery 1
- Power Supply Tolerance
- Ground
- Chip Enable Input
- Chip Enable Output
- + Battery 2
- + Supply
- No Connect
DESCRIPTION
The DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem of
converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance
condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and
the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a low-
leakage CMOS process which affords precise voltage detection at extremely low battery consumption.
The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining the
DS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation
can be achieved.
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The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM.
First, a switch is provided to direct power from the battery or the incoming supply (V
CCI
) depending on
which is greater. This switch has a voltage drop of less than 0.3V.
The second function which the nonvolatile controller provides is power-fail detection. The DS1210
constantly monitors the incoming supply. When the supply goes out of tolerance, a precision comparator
detects power-fail and inhibits chip enable (
CEO
).
The third function of write protection is accomplished by holding the
CEO
output signal to within 0.2
volts of the V
CCI
or battery supply. If
CE
input is low at the time power-fail detection occurs, the
CEO
output is kept in its present state until
CE
is returned high. The delay of write protection until the current
memory cycle is completed prevents the corruption of data. Power-fail detection occurs in the range of
4.75 volts to 4.5 volts with the tolerance (TOL) pin grounded. If TOL in connected to V
CCO
, then power-
fail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions
CEO
will
follow
CE
with a maximum propagation delay of 20ns.
The fourth function the DS1210 performs is a battery status warning so that potential data loss is avoided.
Each time that the circuit is powered up the battery voltage is checked with a precision comparator. If the
battery voltage is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore,
be determined by performing a read cycle after power-up to any location in memory, verifying that
memory location content. A subsequent write cycle can then be executed to the same memory location
altering the data. If the next read cycle fails to verify the written data, then the batteries are less than 2.0V
and data is in danger of being corrupted.
The fifth function of the nonvolatile controller provides for battery redundancy. In many applications,
data integrity is paramount. In these applications it is often desirable to use two batteries to ensure
reliability. The DS1210 controller provides an internal isolation switch which allows the connection of
two batteries. During battery backup operation the battery with the highest voltage is selected for use. If
one battery should fail, the other will take over the load. The switch to a redundant battery is transparent
to circuit operation and to the user. A battery status warning will occur when the battery in use falls below
2.0 volts. A grounded V
BAT2
pin will not activate a battery-fail warning. In applications where battery
redundancy is not required, a single battery should be connected to the BAT1 pin, and the BAT2 battery
pin must be grounded. The nonvolatile controller contains circuitry to turn off the battery backup. This is
to maintain the battery(s) at its highest capacity until the equipment is powered up and valid data is
written to the SRAM. While in the freshness seal mode the
CEO
and V
CCO
will be forced to V
OL
. When
the batteries are first attached to one or both of the V
BAT
pins, V
CCO
will not provide battery back-up until
V
CCI
exceeds V
CCTP
, as set by the TOL pin, and then falls below V
BAT
.
Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section
A shows the connections necessary to write protect the RAM when V
CC
is less than 4.75 volts and to back
up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when V
CC
is
less than 4.75 volts and to delay its restart on power-up to prevent spurious writes.
OPERATION
DS1210
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SECTION A - BATTERY BACKUP
Figure 1
DS1210
BATTERY BACKUP CURRENT DRAIN EXAMPLE
CONSUMPTION
DS1210 I
BAT
RAM I
CC02
Total Drain
100 nA
10
µA
10.1
µA
SECTION B - PROCESSOR RESET
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Voltage Range on Any Pin Relative to Ground
Operating Temperature Range
Storage Temperature Range
Soldering Temperature (reflow, SO)
Lead Temperature (soldering, 10s)
ABSOLUTE MAXIMUM RATINGS
DS1210
-0.3V to +7.0V
0°C to +70°C, -40°C to +85°C for N parts
-55°C to +125°C
+260°C
+300°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
PDIP
SO
Junction-to-Ambient Thermal Resistance (θ
JA
).…………………...…………………………...….110°C/W
Junction-to-Case Thermal Resistance (θ
JC
)…………………………………………………………40°C/W
Junction-to-Ambient Thermal Resistance (θ
JA
).…………………………………………………….70°C/W
Junction-to-Case Thermal Resistance (θ
JC
)…………………………………………………………23°C/W
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board for the SO.
For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
Note 1:
PARAMETER
TOL = GND Supply Voltage
TOL = V
CCO
Supply Voltage
Logic 1 Input
Logic 0 Input
Battery Input
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CCI
V
CCI
V
IH
V
IL
V
BAT1
,
V
BAT2
MIN
4.75
4.5
2.2
-0.3
2.0
4B
TYP
5.0
5.0
MAX
5.5
5.5
V
CC
+0.3
+0.8
4.0
UNITS
V
V
V
V
V
(Note 10)
NOTES
2
2
2
2
2, 3
0B
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Current
Supply Voltage
Supply Current
Input Leakage
Output Leakage
CEO
Output @ 2.4V
CEO
Output @ 0.4V
V
CC
Trip Point (TOL=GND)
V
CC
Trip Point (TOL=V
CCO
)
CEO
Output
V
BAT1
or V
BAT2
Battery Current
Battery Backup Current
@ V
CCO
= V
BAT
– 0.3V
SYMBOL
I
CCI
V
CCO
I
CCO1
I
IL
I
LO
I
OH
I
OL
V
CCTP
V
CCTP
V
OHL
I
BAT
I
CCO2
(Note 10; V
CCI
= 4.75 to 5.5V, TOL = GND)
(V
CCI
= 4.5 to 5.5V, TOL = V
CCO
)
MIN
TYP
MAX
UNITS NOTES
5
mA
4
V
CC
-0.2
V
2
80
mA
5
-1.0
+1.0
µA
-1.0
+1.0
µA
-1.0
mA
6
4.0
mA
6
4.50
4.62
4.74
V
2
4.25
4.37
4.49
V
2
V
BAT
-0.2
V
8
1B
100
50
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nA
µA
3, 4
7, 8
DS1210
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
C
IN
C
OUT
MIN
TYP
MAX
5
7
(T
A
= +25°C)
UNITS NOTES
pF
pF
2B
AC ELECTRICAL CHARACTERISTICS
PARAMETER
CE
Propagation Delay
CE
High to Power-Fail
SYMBOL
t
PD
t
PF
(Note 10; V
CCI
= 4.75V to 5.5V, TOL = GND)
(V
CCI
= 4.5V to 5.5V, TOL = V
CCO
)
MIN
TYP
MAX
UNITS NOTES
5
10
20
ns
6
0
ns
3B
AC ELECTRICAL CHARACTERISTICS
Recovery at Power Up
V
CC
Slew Rate Power-Down
V
CC
Slew Rate Power-Down
V
CC
Slew Rate Power-Up
CE
Pulse Width
t
REC
t
F
t
FB
t
R
t
CE
2
300
10
0
(Note 10; V
CCI
= 4.75V, TOL = GND)
(V
CCI
< 4.5, TOL = V
CCO
)
80
125
ms
µs
µs
µs
1.5
µs
9
NOTES:
2. All voltages are referenced to ground.
3. Only one battery input is required. Unused battery inputs must be grounded.
4. Measured with V
CCO
and
CEO
open.
5. I
CC01
is the maximum average load which the DS1210 can supply to the memories.
6. Measured with a load as shown in Figure 2.
7. I
CC02
is the maximum average load current which the DS1210 can supply to the memories in the battery backup mode.
8. t
CE
max must be met to ensure data integrity on power loss.
9.
CEO
can only sustain leakage current in the battery backup mode.
10. All AC and DC electrical characteristics are valid for the full temperature range. For commercial products, this range is 0
to +70°C. For industrial products (N), this range is -40°C to +85°C.
11. DS1210 is recognized by Underwriters Laboratories (UL) under file E99151.
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