DS1221
Nonvolatile Controller x 4 Chip
www.dalsemi.com
NOT RECOMMENDED FOR NEW DESIGNS, SEE DS1321 DATASHEET INSTEAD.
FEATURES
Converts CMOS RAMs into nonvolatile
memories
Data is automatically protected during power loss
2-to-4 decoder provides for up to 4 CMOS
RAMs
Provides for redundant batteries
Test battery condition on power-up
Full ±10% operating range
Unauthorized access can be prevented with
optional security feature
16-pin 0.3-inch DIP saves PC board space
Optional 16-pin SOIC surface mount package
Optional industrial temperature range of
-40°C to +85°C available
PIN ASSIGNMENT
VCCO
VBAT1
*RST
A
B
*RD
*WE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCCI
VBAT2
CE
CE0
CE1
CE2
CE3
*D/Q
DS1221 16-Pin DIP (300-mil)
See Mech. Drawings Section
VCCO
VBAT1
*RST
A
B
*RD
*WE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCCI
VBAT2
CE
CE0
CE1
CE2
CE3
*D/Q
PIN DESCRIPTION
A, B
CE
CE0
-
CE3
V
BAT1
V
BAT2
*
RST
V
CCI
V
CCO
*
RD
*
WE
*D/Q
- Address Inputs
- Chip Enable Input
- Chip Enable Outputs
- + Battery 1
- + Battery 2
- Reset
- +5V Supply
- RAM Supply
- Read Inpu
- Write Input
- Data Input/Output
DS1221 16-Pin SOIC (300-mil)
See Mech. Drawings Section
*Used with optional security circuit only and must be connected to ground in all other cases.
DESCRIPTION
The DS1221 Nonvolatile Controller x 4 Chip is a CMOS circuit which solves the application problem of
converting CMOS RAMs into nonvolatile memories. Incoming power is monitored for an out-of-
tolerance condition. When such a condition is detected, the chip enable outputs are inhibited to
accomplish write protection and the battery is switched on to supply RAMs with uninterrupted power. An
optional security code prevents unauthorized users from obtaining access to the memory space. The
nonvolatile controller/decoder circuitry uses a low-leakage CMOS process which affords precise voltage
detection at extremely low battery consumption. By combining the DS1221 with up to four CMOS
memories and lithium batteries, nonvolatile operation can be achieved.
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111899
DS1221
CONTROLLER /DECODER OPERATION
The DS1221 nonvolatile controller performs six circuit functions required to decode and battery-backup a
bank of up to four CMOS RAMs. First, a 2-to-4 decoder provides selection of one of four RAMs (see
Figure 1). Second, a switch is provided to direct power from the battery or V
CCI
supply, depending on
which is greater, to the V
CCO
pin. This switch has a voltage drop of less than 0.2V. The third function
which the nonvolatile controller provides is power-fail detection. The DS1221 constantly monitors the
V
CCI
supply. When V
CCI
falls below 4.5 volts, a precision comparator detects the condition and inhibits
the RAM chip enables (
CE0
through
CE3
). The fourth function of write protection is accomplished by
holding all chip enable outputs (
CE0
through
CE3
) to within 0.2 volts of V
CCI
or battery supply. If the
Chip Enable Input (
CE
) is low at the time power-fail detection occurs, the chip enable outputs are kept in
their present state until
CE
is driven high. The delay of write protection until the current memory cycle is
completed prevents the corruption of data. Power failure detection occurs in the range of 4.5 to 4.25 volts.
During nominal supply conditions the chip enable outputs follow the logic of a 2-to-4 decoder. The fifth
function the DS1221 performs is to check battery status to warn of potential data loss. Each time that V
CCI
power is restored the battery voltage is checked with a precision comparator. If the connected battery
voltage is less than 2 volts, the second memory cycle is inhibited. Battery status can, therefore, be
determined by performing a read cycle after power-up to any location in memory, verifying that memory
location content. A subsequent write cycle can then be executed to the same memory location, altering the
data. If the next read cycle fails to verify the written data, the contents of the memories are questionable.
The sixth function of the nonvolatile controller provides for battery redundancy. In many applications,
data integrity is paramount. In these applications it is often desirable to use two batteries to ensure
reliability. The DS1221 provides an internal isolation switch which provides for connection of two
batteries. During battery back-up operation the battery with the highest voltage is selected for use. If one
battery should fail, the other will automatically take over. The switch between batteries is transparent to
the user. A battery status warning will occur if both batteries are less than 2.0 volts. If only one battery is
used, the second battery input must be grounded. Figure 2 illustrates the connections required for the
DS1221 in a typical application.
NONVOLATILE CONTROLLER/DECODER
Figure 1
V
CCI
>=4.5
<4.25
>=4.5
>=4.5
>=4.5
>=4.5
H = High Level
L = Low Level
X = Irrelevant
CE
H
X
L
L
L
L
INPUTS
B
X
X
L
L
H
H
OUTPUTS
A
X
X
L
H
L
H
CE0
CE1
CE2
CE3
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
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DS1221
TYPICAL APPLICATION
Figure 2
SECURITY SEQUENCE
Figure 3
OUTPUT LOAD
Figure 4
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DS1221
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
*
-0.3V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
20 mA
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Supply Voltage
Logic 1 Input
Logic 0 Input
Battery Input
SYMBOL
V
CCI
V
IH
V
IL
V
BAT1
,
V
BAT2
MIN
4.5
2.2
-0.3
2.0
TYP
5.0
MAX
5.5
V
CC
+0.3
+0.8
4.0
(0°C to 70°C)
UNITS
V
V
V
V
NOTES
1
1
1
1, 2
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Current
Supply Voltage
Supply Current
Input Leakage
Output Leakage
CE0
-
CE3
, DQ
Output @ 2.4V
CE0
-
CE3
, DQ
Output @ 0.4V
V
CC
Trip Point
SYMBOL
I
CCI
V
CCO
I
CCO1
I
IL
I
LO
I
OH
I
OL
V
CCTP
4.25
MIN
V
CC
-0.2
-1.0
-1.0
-1.0
(0°C to 70°C; V
CC
= 4.5 to 5.5V)
TYP
MAX
5
80
+1.0
+1.0
UNITS
mA
V
mA
µA
µA
mA
mA
V
NOTES
3
1
4, 10
5
5
1
4.0
4.37
4.50
(0°C to 70°C; V
CC
< 4.25V)
PARAMETER
CE0
-
CE3
Output
V
BAT1
or V
BAT2
Battery Current
Battery Backup Current
@ V
CCO
= V
BAT
- 0.5V
SYMBOL
V
OHL
I
BAT
I
CCO2
MIN
V
CC
-0.2
V
BAT
-0.2
TYP
MAX
0.1
100
UNITS
V
µA
µA
NOTES
3
6, 7, 10
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DS1221
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
C
IN
C
OUT
MIN
TYP
MAX
5
7
(t
A
= 25°C)
UNITS
pF
pF
NOTES
AC ELECTRICAL CHARACTERISTICS
PARAMETER
CE
Propagation Delay
CE
High to Power-Fail
Address Setup
SYMBOL
t
PD
t
PF
t
AS
MIN
5
20
(0°C to 70°C; V
CC
= 4.5 to 5.5V)
TYP
15
MAX
25
0
UNITS
ns
ns
ns
NOTES
5
9
(0°C to 70°C; V
CC
< 4.5V)
PARAMETER
Recovery at Power-Up
V
CC
Slew Rate 4.5 - 4.25V
V
CC
Slew Rate 4.25 - 3V
V
CC
Slew Rate 4.25 - 4.5V
CE
Pulse Width
SYMBOL
t
REC
t
F
t
FB
t
R
t
CE
MIN
2
300
10
0
TYP
5
MAX
10
UNITS
ms
µs
µs
µs
µs
NOTES
1.5
7, 8
NOTES:
1. All voltages are referenced to ground.
2. Only one battery input is required.
3. Measured with V
CCO
and
CE0
-
CE3
open.
4. I
CCO1
is the maximum average load which the DS1221 can supply to the memories.
5. Measured with a load as shown in Figure 4.
6. I
CCO2
is the maximum average load current which the DS1221 can supply to the memories in the
battery back-up mode.
7. Chip enable outputs
CE0
-
CE3
can only sustain leakage current in the battery back-up mode.
8. t
CE
max. must be met to ensure data integrity on power loss.
9. t
AS
is only required to keep the decoder outputs glitch-free. While CE is low, the outputs (
CE0
-
CE3
)
will be defined by inputs A and B with a propagation delay of t
PD
from an A or B input change.
10. For applications where higher currents are required, please see the DS1259 Battery Manager Chip
data sheet.
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