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CY28401OC

Description
PLL Based Clock Driver, 28401 Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48
Categorylogic    logic   
File Size177KB,13 Pages
ManufacturerSilicon Laboratories Inc
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CY28401OC Overview

PLL Based Clock Driver, 28401 Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48

CY28401OC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSilicon Laboratories Inc
Parts packaging codeSSOP
package instructionSSOP,
Contacts48
Reach Compliance Codeunknown
Other featuresPLL BYPASS-CONFIGURABLE
series28401
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeR-PDSO-G48
length15.875 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals48
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)0.25 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.2 ns
Maximum seat height2.794 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.5057 mm
Base Number Matches1
CY28401
100 MHz Differential Buffer for PCI Express and SATA
Features
• CK409 or CK410 companion buffer
• Eight differential 0.7V clock pairs
• Individual OE controls
• Low CTC jitter (< 50 ps)
• Programmable bandwidth
• SRC_STOP# power management control
• SMBus Block/Byte/Word Read and Write support
• 3.3V operation
• PLL Bypass-configurable
• Divide by 2 programmable
• 48-pin SSOP package
Functional Description
The CY28401 is a differential buffer and serves as a
companion device to the CK409 or CK410 clock generator.
The device is capable of distributing the Serial Reference
Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
Pin Configuration
SRC_DIV2#
VDD
VSS
SRCT_IN
SRCC_IN
OE_0
OE_3
DIFT0
DIFCO
VSS
VDD
DIFT1
DIFC1
OE_1
OE_2
DIFT2
DIFC2
VSS
VDD
DIFT3
DIFC3
PLL/BYPASS#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_A
VSS_A
IREF
LOCK
OE_7
OE_4
DIFT7
DIFC7
VSS
VDD
DIFT6
DIFC6
OE_6
OE_5
DIFT5
DIFC5
VSS
VDD
DIFT4
DIFC4
HIGH_BW#
SRC_STOP#
PWRDWN#
VSS
DIFT0
OE_[0:7]
SRC_STOP#
PWRDWN#
DIFC0
Output
Control
DIFT1
DIFC1
DIFT2
SCLK
SDATA
SRC_DIV2#
PLL/BYPASS#
SMBus
Controller
Output
Buffer
DIFC2
DIFT3
DIFC3
DIFT4
DIFC4
DIFT5
DIFC5
CY28401
SRCT_IN
SRCC_IN
DIV
HIGH_BW#
DIFT6
DIFC6
PLL
DIFT7
DIFC7
LOCK
48 SSOP
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 13
www.SpectraLinear.com
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