DS1236A
MicroManager Chip
www.maxim-ic.com
FEATURES
Holds microprocessor in check during power
transients
Halts and restarts an out-of-control
microprocessor
Monitors pushbutton for external override
Warns microprocessor of an impending power
failure
Converts CMOS SRAM into nonvolatile
memory
Unconditionally write protects memory when
power supply is out of tolerance
Consumes less than 100 nA of battery current
at 25°C
Controls external power switch for high
current applications
Accurate 10% power supply monitoring
Optional 5% power supply monitoring
designated DS1236A-5
Provides orderly shutdown in nonvolatile
microprocessor applications
Supplies necessary control for low-power
“stop mode” in battery operated hand-held
applications
Standard 16-pin DIP or space-saving 16-pin
SOIC
Optional industrial temperature range -40°C
to +85°C
PIN ASSIGNMENT
VBAT
VCCO
VCC
GND
PF
PF
WC/SC
RC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
RST
PBRST
CEI
CEO
ST
NMI
IN
VBAT
VCCO
VCC
GND
PF
PF
WC/SC
RC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
RST
PBRST
CEI
CEO
ST
NMI
IN
16-Pin DIP (300-mil)
See Mech. Drawings Section
16-Pin SOIC (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
V
BAT
V
CCO
V
CC
GND
PF
PF
WC/
SC
RC
IN
NMI
ST
CEO
CEI
PBRST
RST
RST
- +3-Volt Battery Input
- Switched SRAM Supply Output
- +5-Volt Power Supply Input
- Ground
- Power-Fail (Active High)
- Power-Fail (Active Low)
- Wake-Up Control (Sleep)
- Reset Control
- Early Warning Input
- Non-Maskable Interrupt
- Strobe Input
- Chip Enable Output
- Chip Enable Input
- Pushbutton Reset Input
- Reset Output (Active Low)
- Reset Output (Active High)
DESCRIPTION
The DS1236A MicroManager Chip provides all the necessary functions for power supply monitoring,
reset control, and memory backup in microprocessor-based systems. A precise internal voltage reference
and comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the
microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
write protects external memory. The DS1236A also provides early warning detection of a user-defined
threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset
1 of 20
011107
DS1236A
input which is debounced and activates reset outputs. An internal watchdog timer can also force the reset
outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Reset control
and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and start-up in
battery backup and battery operated applications. A block diagram of the DS1236A is shown in NO TAG.
PIN DESCRIPTION
PIN NAME
V
BAT
V
CCO
V
CC
PF
PF
DESCRIPTION
+3V battery input provides nonvolatile operation of control functions.
V
CC
output for nonvolatile SRAM applications.
+5V primary power input.
Power-fail indicator, active high, used for external power switching as shown in NO
TAG.
Power-fail indicator, active low.
Wake-up and Sleep control. Invokes low-power mode.
Reset control input. Determines reset output . Normally low for NMOS processors and
high for battery backed CMOS processors.
Early warning power-fail input. This voltage sense point can be tied (via resistor
divider) to a user-selected voltage.
Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending
power failure.
Strobe input. A high-to-low transition will reset the watchdog timer, indicating that
software is still in control.
Chip enable output. Used with nonvolatile SRAM applications.
Chip enable input.
Pushbutton reset input.
Active low reset output.
Active high reset output.
WC/
SC
RC
IN
NMI
ST
CEO
CEI
PBRST
RST
RST
PROCESSOR MODE
A distinction is often made between CMOS and NMOS processor systems. In a CMOS system, power
consumption may be a concern, and nonvolatile operation is possible by battery backing both the SRAM
and the CMOS processor. All resources would be maintained in the absence of V
CC
. A power-down reset
is not issued since the low-power mode of most CMOS processors (Stop) is terminated with a Reset. A
pulsed interrupt (
NMI
) is issued to allow the CMOS processor to invoke a sleep mode to save power. For
this case, a power-on reset is desirable to wake up and initialize the processor. The CMOS mode is
invoked by connecting RC to V
CCO
.
An NMOS processor consumes more power, and consequently may not be battery backed. In this case, it
is desirable to notify the processor of a power-fail, then keep it in reset during the loss of V
CC
. This avoids
intermittent or aberrant operation. On power-up, the processor will continue to be reset until V
CC
reaches
an operational level to provide an orderly start. The NMOS mode is invoked by connecting RC to ground.
2 of 20
DS1236A
POWER MONITOR
The DS1236A employs a band gap voltage reference and a precision comparator to monitor the 5-volt
supply (V
CC
) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RST and
RST
outputs are driven to the active state. The V
CC
trip point (V
CCTP
) is set for 10% operation so that the
RST and
RST
outputs will become active as V
CC
falls below 4.5 volts (4.37 typical). The V
CCTP
for the
5% operation option (DS1236A-5) is set for 4.75 volts (4.62 typical). The RST and
RST
signals are
excellent for microprocessor reset control, as processing is stopped at the last possible moment of in-
tolerance V
CC
. On power-up, the RST and
RST
signals are held active for a minimum of 25 ms (100 ms
typical) after V
CCTP
is reached to allow the power supply and microprocessor to stabilize. Note: The
operation described above is obtained with the reset control pin (RC) connected to GND (NMOS mode).
Please review the reset control section for more information.
WATCHDOG TIMER
The DS1236A provides a watchdog timer function which forces the RST and
RST
signals to the active
state when the strobe input (
ST
) is not stimulated for a predetermined time period. This time period is 400
ms typically with a maximum timeout of 600 ms. The watchdog timeout period begins as soon as RST
and
RST
are inactive. If a high-to-low transition occurs at the
ST
input prior to timeout, the watchdog
timer is reset and begins to time out again. The
ST
input timing is shown in NO TAG. To guarantee the
watchdog timer does not time out, a high-to-low transition on
ST
must occur at or less than 100 ms
(minimum timeout) from a reset. If the watchdog timer is allowed to time out, the RST and
RST
outputs
are driven to the active state for 25 ms minimum. The
ST
input can be derived from microprocessor
address, data, and/or control signals. Under normal operating conditions, these signals would routinely
reset the watchdog timer prior to timeout. If the watchdog timer is not required, two methods have been
provided to disable it.
Permanently grounding the IN pin in the CMOS mode (RC=1) will disable the watchdog. In normal
operation with RC=1, the watchdog is disabled as soon as the IN pin is below V
TP
. With IN grounded, an
NMI
output will occur only at power-up, or when the
ST
pin is strobed. As shown in the NO TAG, a
falling edge on
ST
will generate an
NMI
when IN is below V
TP
. This allows the processor to verify that
power is between V
TP
and V
CCTP
, as an
NMI
will be returned immediately after the
ST
strobe. The
watchdog timer is not affected by the IN pin when in NMOS mode (RC=0).
If the
NMI
signal is required to monitor supply voltages, the watchdog may also be disabled by leaving
the
ST
input open. Independent of the state of the RC pin, the watchdog is also disabled as soon as V
CC
falls to V
CCTP
.
PUSHBUTTON RESET
An input pin is provided on the DS1236A for direct connection to a pushbutton. The pushbutton reset
input requires an active low signal. Internally, this input is pulled high by a 10k resistor whenever V
CC
is
greater than V
BAT
. The
PBRST
pin is also debounced and timed such that the RST and
RST
outputs are
driven to the active state for 25 ms minimum. This 25 ms delay begins as the pushbutton is released from
a low level. A typical example of the power monitor, watchdog timer, and pushbutton reset connections
are shown in NO TAG. The
PBRST
input is disabled whenever the IN pin voltage level is less than V
TP
and the reset control (RC) is tied high (CMOS mode). The
PBRST
input is also disabled whenever V
CC
is
below V
BAT
. Timing of the
PBRST
-generated RST is illustrated in Figure 1.
3 of 20
DS1236A
NON-MASKABLE INTERRUPT
The DS1236A generates a non-maskable interrupt
NMI
for early warning of power failure to a
microprocessor. A precision comparator monitors the voltage level at the IN pin relative to a reference
generated by the internal band gap. The IN pin is a high-impedance input allowing for a user-defined
sense point. An external resistor voltage divider network (NO TAG) is used to interface with high voltage
signals. This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage
level closer to the main system power input. Since the IN trip point V
TP
is 2.54 volts, the proper values
for R1 and R2 can be determined by the equation as shown in NO TAG. Proper operation of the
DS1236A requires that the voltage at the IN pin be limited to V
IN
. Therefore, the maximum allowable
voltage at the supply being monitored (V
MAX
) can also be derived as shown in NO TAG. A simple
approach to solving this equation is to select a value for R2 high enough to keep power consumption low,
and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point
in a power supply system, maximizing the amount of time for microprocessor shutdown between
NMI
and RST or
RST
.
When the supply being monitored decays to the voltage sense point, the DS1236A pulses the
NMI
output
to the active state for a minimum of 200
μs.
The
NMI
power-fail detection circuitry also has built-in time
domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33
μs/cycle).
Three consecutive samplings of
out-of-tolerance supply (below V
SENSE
) must occur at the IN pin to activate
NMI
. Therefore, the supply
must be below the voltage sense point for approximately 100
μs
or the comparator will reset. In this way,
power supply noise is removed from the monitoring function, preventing false trips. During a power-up,
any detected IN pin levels be low V
TP
by the comparator are disabled from reaching the
NMI
pin until
V
CC
rises to V
CCTP
. As a result, any potential
NMI
pulse will not be initiated until V
CC
reaches V
CCTP
.
Removal of an active low level on the
NMI
pin is controlled by either an internal timeout (when IN pin is
less than V
TP
) or by the subsequent rise of the IN pin above V
TP
. The initiation and removal of the
NMI
signal during power-up results in an
NMI
pulse of from 0
μs
minimum to 500
μs
maximum, depending
on the relative voltage relationship between V
CC
and the IN pin voltage. As an example, when the IN pin
is tied to ground during power-up, the internal timeout will result in a pulse of 200
μs
minimum to 500
μs
maximum. In contrast, if the IN pin is tied to V
CCO
during power-up,
NMI
will not produce a pulse on
power-up. Note that a fast-slewing power supply may cause the
NMI
to be virtually nonexistent on
power-up. This is of no consequence, however, since an RST will be active.
4 of 20
DS1236A
DS1236A FUNCTIONAL BLOCK DIAGRAM
Figure 1
5 of 20
stm32/stm8
京公网安备 11010802033920号
EEWORLD
