MT48H16M32L2B5-8 TR datasheet, PDF

Datasheet> All Categories > storage> MT48H16M32L2B5-8 TR

MT48H16M32L2B5-8 TR: DescriptionIC sdram 512mbit 125mhz 90vfbga; Categorystorage; File Size266KB，10 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

Download Datasheet Parametric View All

MT48H16M32L2B5-8 TR Overview

IC sdram 512mbit 125mhz 90vfbga

MT48H16M32L2B5-8 TR Parametric

Parameter Name	Attribute value
Datasheets
MT48(LC,V,H)16M32L2
Product Photos
MT46H32M32LFB5-6 IT	B TR
Standard Package	1,000
Category	Integrated Circuits (ICs)
Family	Memory
Packaging	Tape & Reel (TR)
Format - Memory	RAM
Memory Type	Mobile LPSDR SDRAM
Memory Size	512M (16M x 32)
Speed	125MHz
Interface	Parallel
Voltage - Supply	1.7 V ~ 1.9 V
Operating Temperature	0°C ~ 70°C
Package / Case	90-VFBGA
Supplier Device Package	90-VFBGA (8x13)

Preview

Download Datasheet

View All

512Mb : x32 TwinDie Mobile SDRAM Addendum

Features

Mobile SDRAM

MT48LC16M32L2 – 4 Meg x 32 x 4 Banks

MT48V16M32L2 – 4 Meg x 32 x 4 Banks

MT48H16M32L2 – 4 Meg x 32 x 4 Banks

Features

•

Low voltage power supply

Partial array self refresh power-saving mode

Temperature compensated self refresh (TCSR)

Deep power-down mode

Programmable output drive strength

Fully synchronous; all signals registered on positive

edge of system clock

Internal pipelined operation; column address can

be changed every clock cycle

Internal banks for hiding row access/precharge

Programmable burst lengths: 1, 2, 4, 8, or full page

Auto precharge, includes concurrent auto

precharge, and auto refresh modes

Self refresh mode; standard and low power

64ms, 8,192-cycle refresh

LVTTL-compatible inputs and outputs

Operating temperature range

Industrial (-40°C to +85°C)

Supports CAS latency of 1, 2, 3

Addendum Changes

The standard 256Mb SDRAM Mobile x32 data sheets

should be referenced for a complete description of

SDRAM functionality and operating modes. This

addendum data sheet will concentrate on the key dif-

ferences required to support the enhanced options of

the TwinDie configuration.

The Micron 256Mb Mobile X32 data sheet provides full

specifications and functionality unless specified

herein.

Table 1:

Speed

Grade

-8

-10

Key Timing Parameters

Clock

Frequency

125 MHz

100 MHz

Access Time Access Time

at CL = 3

at CL = 2

7.5ns

8.5ns

Table 2:

Configuration

16 Meg x 32

4 Meg x 32 x 4 banks

8K (A0–A12)

4 (BA0, BA1)

512 (A0–A8)

Options

• V

3.3V/3.3V

2.5V/2.5V

1.8V/1.8V

• Configuration

16M32 stacked die

• Package/ballout

Plastic package 90-ball FBGA

(8mm x 13mm) (standard)

Plastic package 90-ball FBGA

(8mm x 13mm) (lead-free)

• Timing (cycle time)

8ns at CL3 (125 MHz)

10ns at CL3 (100 MHz)

• Temperature

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Marking

Architecture

Configuration

Refresh Count

Row Addressing

Bank Addressing

Column Addressing

-8

-10

No Marking

PDF: 09005aef817f1b8c/Source: 09005aef818112f1

512Mb Mobile SDRAM_TwinDie_x32.fm - Rev. C 6/05 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb : x32 TwinDie Mobile SDRAM Addendum

General Description

The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing

536,870,912 bits. It is internally configured by stacking two 256Mb, 8 Meg x 32 devices.

Each of these 256Mb devices is configured as a quad bank DRAM with a synchronous

interface. They are organized with 32 DQs with 4 banks of 67,108,864 bits, comprising of

8,192 rows by 512 columns by 32 bits wide.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank; A0-A12 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while accessing one of the other three banks

will hide the precharge cycles and provide seamless, high-speed, random-access opera-

tion.

The 512Mb SDRAM is designed to operate in 3.3V, 2.5V, and 1.8V memory systems. An

auto refresh mode is provided, along with a power-saving, power-down mode. All inputs

and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the abil-

ity to synchronously burst data at a high data rate with automatic column-address gen-

eration, the ability to interleave between internal banks to hide precharge time, and the

capability to randomly change column addresses on each clock cycle during a burst

access.

Prior to normal operation, the SDRAM must be initialized. The following sections pro-

vide detailed information covering die intitialization, register definition, command

descriptions, and device operation on a per die basis unless otherwise noted.

This addendum documents any variances for the 512Mb: x32 Mobile SDRAM from the

256Mb: x32 Mobile SDRAM specification. Please refer to the 256Mb: x32 Mobile SDRAM

data sheet on Micron’s Web site for additional details on the part functionality.

Commands

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is non-

persistent, so it must be issued each time a refresh is required. All active banks must be

PRECHARGED prior to issuing a AUTO REFRESH command. The AUTO REFRESH com-

mand should not be issued until the minimum

RP has been met after the PRECHARGE

command as shown in the operations section.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an AUTO REFRESH command. The 512Mb TwinDie™ Mobile

SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (

REF). Providing a distributed

PDF: 09005aef817f1b8c/Source: 09005aef818112f1

512Mb Mobile SDRAM_TwinDie_x32.fm - Rev. C 6/05 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Recommended Resources

RTS998 (8-tone) circuit

Adjustable double-limit over-temperature annunciator circuit

Pulse charger circuit diagram with self-detection function

Small DC-DC converter

Automobile electronic ignition circuit

Xiaxin A8 mobile phone troubleshooting diagram 2

Can the smallest AT89S5X-compatible board download AVR?: I have been learning 51 MCU design for a while, and I plan to learn AVR. Since I don't have small capacitors and I have an old 51 minimum system board, I bought a pin-compatible avr, model AT90S8515.....; CMLite Microchip MCU

Attention job seekers after the Chinese New Year! 25 of the weirdest IT interview questions in 2013, how many do you know?: [p=22, null, left][color=#494949][font=宋体, Arial, Helvetica, sans-serif][size=3][color=#444444]Interviews at high-tech companies are surprisingly difficult. They not only test the interviewer's techni...; qwqwqw2088 Talking about work

CPLD counting problem: I used two counters of CPLD to count the 150M and 26M crystal oscillators. When the frequency of 26M overflowed from 0 to 16 bits, I took the value of the 150M counter and sent it to MCU through SPI, ...; eadge Embedded System

LTC3631EMS8E 12V to 5V circuit schematic: LTC3631EMS8E 12V to 5V circuit schematic, 12V to 5V circuit schematic, you can use...; Jacktang Analogue and Mixed Signal

You don’t understand the willfulness of programmers: [p=25, null, left][font=微软雅黑][size=3][color=#000000]Every day when I open my Moments, it’s like traveling through space! Do you really think that watching a high-IQ sci-fi movie will improve your stat...; error_echo Talking

Let's talk about the composition and functions of each component of the S3C2440A Block Diagram schematic diagram......: [img]D:\1.GIF][/img][img=D:\2.GIF][/img][img=D:\3.GIF[/img]...; xingcard Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components