DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port
October 1986
Revised April 2000
DM74AS286
9-Bit Parity Generator/Checker
with Bus-Driver Parity I/O Port
General Description
These universal, 9-bit parity generators/checkers utilize
advanced Schottky high performance circuitry and feature
odd/even outputs to facilitate operation of either odd or
even parity applications. The word length capability is eas-
ily expanded by cascading.
The DM74AS286 can be used to upgrade the performance
of most systems utilizing the DM74AS280 parity generator/
checker. Although the DM74AS286 is implemented without
expander inputs, the corresponding function is provided by
the availability of an input pin XMIT. XMIT is a control line
which makes parity error output active and parity an input
port when HIGH; when LOW, parity error output is inactive
and parity becomes an output port. In addition, parity I/O
control circuitry contains a feature to keep the I/O port in
the 3-STATE during power UP or DOWN to prevent bus
glitches.
Features
s
PNP inputs to reduce bus loading
s
Generates either odd or even parity for nine data lines
s
Inputs are buffered to lower the drive requirements
s
Can be used to upgrade existing systems using MSI
parity circuits
s
Cascadable for n-bits
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full
temperature and V
CC
range
s
A parity I/O portable to drive bus
Ordering Code:
Order Number
DM74AS286M
DM74AS286N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Number of Inputs
(A thru I)
that are HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
0, 2, 4, 6, 8
0, 2, 4, 6, 8
1, 3, 5, 7, 9
1, 3, 5, 7, 9
L
=
LOW Logic Level
H
=
HIGH Logic Level
N/A
=
Not Applicable
Parity I/O
Input Output
N/A
N/A
H
L
H
L
H
L
N/A
N/A
N/A
N/A
Parity
XMIT Error
L
L
H
H
H
H
H
H
H
L
L
H
Mode
of
Operation
Parity
Generator
Parity
Checker
Parity
Checker
© 2000 Fairchild Semiconductor Corporation
DS006305
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DM74AS286
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
Typical
θ
JA
N Package
M Package
77.0°C/W
108.0°C/W
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Operating Free-Air Temperature
Parity I/O
Parity Error
Parity I/O
Parity Error
0
Parameter
Min
4.5
2
0.8
−15
−2
48
20
70
Typ
5
Max
5.5
Units
V
V
V
mA
mA
mA
mA
°C
Electrical Characteristics
over recommended free-air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25°C.
Symbol
V
IK
V
OH
V
OL
I
I
I
IH
I
IL
I
O
I
CC
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level Output Voltage
Input Current at Maximum
Input Voltage
HIGH Level Input Current
LOW Level Input Current
Output Drive Current
Supply Current
Conditions
V
CC
=
4.5V, I
IN
= −18
mA
I
OH
=
Max, V
CC
=
4.5V
V
CC
=
4.5V to 5.5V, I
OH
= −2
mA
V
CC
=
4.5V, I
OL
=
Max
V
CC
=
5.5V, V
IH
=
7V
(V
I
=
5.5V for Parity I/O)
V
CC
=
5.5V
V
IH
=
2.7V (Note 2)
V
CC
=
5.5V, V
IL
=
0.4V (Note 2)
V
CC
=
5.5V, V
OUT
=
2.25V
V
CC
=
5.5V, Transmit Mode
XMIT
=
LOW
Receive Mode
XMIT
=
HIGH
Note 2:
For I/O ports, the parameters I
IH
and I
IL
include the OFF-state current, I
OZH
and I
OZL
.
Min
2.4
V
CC
−
2
Typ
3.2
0.35
Max
−1.2
Units
V
V
V
0.5
0.1
V
mA
µA
mA
mA
mA
mA
Others
Parity I/O
−30
20
50
−0.5
−112
43
50
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2
DM74AS286
Switching Characteristics
over recommended supply and temperature range
Symbol
Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay Time
from LOW-to-HIGH Level Output
Propagation Delay Time
from HIGH-to-LOW Level Output
Propagation Delay Time
from LOW-to-HIGH Level Output
Propagation Delay Time
from HIGH-to-LOW Level Output
Propagation Delay Time
from LOW-to-HIGH Level Output
Propagation Delay Time
from HIGH-to-LOW Level Output
t
PZL
t
PLZ
t
PZH
t
PHZ
Output Enable Time to LOW Level
Output Disable Time from LOW Level
Output Disable Time from HIGH Level
Output Enable Time to HIGH Level
From
Any Data Input
Any Data Input
Any Data Input
Any Data Input
Parity I/O
Parity I/O
XMIT
XMIT
XMIT
XMIT
To
Parity I/O
Parity I/O
Parity Error
Parity Error
Parity Error
Parity Error
Parity I/O
Parity I/O
Parity I/O
Parity I/O
Min
3
3
3
3
3
3
3
3
3
3
Max
15
14
16.5
16.5
9
9
16
10
13
11.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Typical Applications
Number of
Inputs that
are Logic “1”
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
Even
Odd
Parity
Result
Output
L
H
FIGURE 1. Dedicated 10-Bit Parity Sensing Configuration
3
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