DM74AS280 9-Bit Parity Generator/Checker
October 1986
Revised March 2000
DM74AS280
9-Bit Parity Generator/Checker
General Description
These universal, 9-bit parity generators/checkers utilize
advanced Schottky high performance circuitry and feature
odd/even outputs to facilitate operation of either odd or
even parity applications. The word length capability is eas-
ily expanded by cascading.
The DM74AS280 can be used to upgrade the performance
of most systems utilizing the ’180 parity generator/checker.
Although the DM74AS280 is implemented without
expander inputs, the corresponding function is provided by
the availability of an input at pin 4 and no internal connec-
tion at pin 3. This permits the DM74AS280 to be substi-
tuted for the ’180 in existing designs to produce identical
function even if DM74AS280s are mixed with existing
’180s.
Features
s
Generates either odd or even parity for nine data lines
s
Inputs are buffered to lower the drive requirements
s
Can be used to upgrade existing systems using MSI
parity circuits
s
Cascadable for N-bits
s
Advanced oxide-isolated, ion-implanted Schottky
TTL process
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full
temperature and V
CC
range
Ordering Code:
Order Number
DM74AS280M
DM74AS280N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Number of Inputs (A thru I)
that are HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
L
=
LOW State
H
=
HIGH State
Outputs
∑Even
H
L
∑Odd
L
H
© 2000 Fairchild Semiconductor Corporation
DS006303
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DM74AS280
Logic Diagram
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2
DM74AS280
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
Typical
θ
JA
N Package
M Package
77.0°C/W
108.0°C/W
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free-Air Operating Temperature
0
Parameter
Min
4.5
2
0.8
−2
20
70
Typ
5
Max
5.5
Units
V
V
V
mA
mA
°C
Electrical Characteristics
Over recommended free-air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25°C.
Symbol
V
IK
V
OH
V
OL
I
I
I
IH
I
IL
I
O
I
CC
Parameter
Input Clamp Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Output Drive Current
Supply Current
Conditions
V
CC
=
4.5V, I
I
= −18
mA
I
OH
= −2
mA, V
CC
=
4.5V to 5.5V
V
CC
=
4.5V, I
OL
=
Max
V
CC
=
5.5V, V
IH
=
7V
V
CC
=
5.5V, V
IH
=
2.7V
V
CC
=
5.5V, V
IL
=
0.4V
V
CC
=
5.5V, V
O
=
2.25V
V
CC
=
5.5V
−30
25
V
CC
−
2
0.35
0.5
0.1
20
−0.5
−112
40
Min
Typ
Max
−1.2
Units
V
V
V
mA
µA
mA
mA
mA
Switching Characteristics
over recommended operating free air temperature range
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Propagation Delay Time,
LOW-to-HIGH Level Output
Propagation Delay Time,
HIGH-to-LOW Level Output
Propagation Delay Time,
LOW-to-HIGH Level Output
Propagation Delay Time,
HIGH-to-LOW Level Output
Data
∑Odd
C
L
=
50 pF,
R
L
=
500Ω
Conditions
V
CC
=
4.5V to 5.5V,
From
Data
To
∑Even
Min
3
3
3
3
Max
12
11
12
11.5
Units
ns
ns
ns
ns
3
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DM74AS280
Typical Applications
Three DM74AS280s can be used to implement a 25-line
parity generator/checker.
As an alternative, the outputs of two or three parity genera-
tors/checkers can be decoded with a 2-input (AS86) or 3-
input (S135) exclusive-OR gate for 18 or 27-line parity
applications.
Longer word lengths can be implemented by cascading
DM74AS280s. As shown in Figure 2, parity can be gener-
ated for word lengths up to 81 bits.
FIGURE 1. 25-Line
Parity/Generator Checker
FIGURE 2. 81-Line Parity/Generator Checker
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4
DM74AS280
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M14A
5
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