31FMN-SSTK-A(LF)(SN) datasheet, PDF

Datasheet> All Categories > The connector> The connector> 31FMN-SSTK-A(LF)(SN)

31FMN-SSTK-A(LF)(SN): DescriptionCard Edge Connector; CategoryThe connector The connector; File Size97KB，3 Pages; ManufacturerJST

Download Datasheet Parametric View All

31FMN-SSTK-A(LF)(SN) Overview

Card Edge Connector

31FMN-SSTK-A(LF)(SN) Parametric

Parameter Name	Attribute value
Reach Compliance Code	unknow
Connector type	FFC/FPC CONNECTOR
Base Number Matches	1

Preview

Download Datasheet

View All

1.0mmピッチ

FMN

CONNECTOR

1.0mm pitch/Connectors for FFC

Emboss Tape

NON-

Specifications –––––––––––––––––––

• Current rating: 0.5 A DC

• Voltage rating: 50 V DC

• Temperature range: -25˚C to +85˚C

(including temperature rise in applying

electrical current)

• Contact resistance: Initial value/ 30 mΩ max.

After environmental tests/ 50 mΩ max.

• Insulation resistance: 500 MΩ min.

• Withstanding voltage: 500 VAC/minute

• Applicable FFC: Conductor pitch/ 1.0 mm

Conductor width/ 0.7 mm

Mating part thickness/ 0.3

0.05 mm

• Applicable PC board thickness: 1.6 mm

Note

: FFC

to be actually used should be checked for applicability.

Through-hole type

SMT type

• Compact

• Low insertion force

• Both through-hole and SMT types are

available

• Embossed tape for automatic mounting

* Refer to "General Instruction and Notice when using

Terminals and Connectors" at the end of this catalog.

* Contact JST for details.

* Compliant with RoHS.

Standards ––––––––––––––––––––––

Certified LR20812

Top entry type

<In-line>

Recognized E60389

PC board layout and Assembly layout

<Through-hole type>

Top entry type

Normal type

±0.05

0.75

±0.05

Normal type

±0.05

0.2

1.8

2.7

0.7

4.4

Odd number

circuits

±0.05

Contact

point

Circuit No.1

1.8

1.9

Even number

circuits

0.7

1.2

Reverse type

5.1

±0.05

Circuit No.1

0.6

±0.05

Circuit No.1

0.6

±0.05

Circuit No.1

±0.05

Odd number

circuits

Even number

circuits

±0.05

0.75

±0.05

Circuit No.1

0.6

0.65

1.9

±0.05

Circuit No.1

0.2

1.9

0.7

Normal type

Circuit No.1

±0.05

φ0.75

±0.05

1.8

0.7

1.2

0.6

±0.05

Odd number

circuits

Even number

circuits

±0.05

Side entry type

5.1

1.2 1.2

0.2

5.1

1.8

Contact

point

Reverse type

±0.05

φ0.75

±0.05

Contact

point

3.05

5.1

Even number

circuits

Odd number

circuits

Circuit No.1

±0.05

2.65

±0.05

0.6

Circuit No. 1

±0.05

Note:

1. The above figure is the figure viewed from the connector mounting side.

2. Tolerances are non-cumulative:

0.05 mm for all centers.

3. Hole dimensions differ according to the type of PC board and piercing

method. The dimensions above should serve as a guideline.

Contact JST for details.

Note:

1. The above figure is the figure viewed from the connector mounting side.

2. Tolerances are non-cumulative:

0.05 mm for all centers.

3. The dimensions above should serve as a guideline.

Contact JST for details.

1.2

1.7

1.8

Side entry type

1.2

5.15

Reverse type

1.7

Contact

point

Recommended Resources

One of the irreversible speed regulation circuits for small DC motors

Use HFC3040 to make a six-way lantern controller

5-digit LED real-time display circuit

7x9 level adjustable timer circuit diagram

A 12-in-1 remote control circuit, the IC is EM78P156

Cascade gain programmable amplifier circuit

I have received the LPC800mini board. Thank you! Let's talk in our spare time.: It looks quite sophisticated. I haven't looked at the detailed information yet. I don't know if it is the same as the STM M0 kit. Can it be downloaded directly using USB? I will explore it when I have...; wgsxsm NXP MCU

MSP430 G2553 Launchpad Capacitance Measurement Test Code: 四、测试代码 main.c程序：复制代码1 // C meter 2015.9.262 //3 // P1.5(TA0.0) --[||||]----------- P1.4(CA3)4 //R=10kOhm|5 //-----6 //cap -----7 //|8 //GND10 /////////////////////////////////////////1112 #include "io...; fish001 Microcontroller MCU

In the always block of Verilog, are there both level and edge triggers?: How can we have both level and edge triggering in the always block of Verilog? For example, always@(a or b or c) I want a to be edge triggered. How can I implement it?...; jokeboy999 FPGA/CPLD

Show the process of WEBENCH design + step-down 3.3V: Show the process of WEBENCH design + step-down 3.3V When we often do DEMO testing 430, we directly draw power from the 5V USB, which is convenient! Enter the [color=#555555]WEBENCH[/color][size=14px] ...; 蓝雨夜 Analogue and Mixed Signal

Question: In Windows Mobile 6, how do I obtain the properties of a media file and its associated information?: I am now troubled by this problem... Here I need to get the attribute information of various multimedia files (mp3, mp4, 3gp, etc.) on the mobile phone (or the simulator), such as their format informa...; chenjian3 Embedded System

Renesas R5F10268 burning problem: I can use Flash programmer's Autoprodure to burn the program (display the percentage and PASS results), but it does not run normally. However, I can use the development software (CS+) to download the ...; dirty Renesas Electronics MCUs

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components