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SIT3542ACA2C2301SY340.000001

Description
LVDS Output Clock Oscillator, 340.000001MHz Nom, QFN, 10 PIN
CategoryPassive components    oscillator   
File Size1MB,49 Pages
ManufacturerSiTime
Environmental Compliance
Download Datasheet Parametric View All

SIT3542ACA2C2301SY340.000001 Overview

LVDS Output Clock Oscillator, 340.000001MHz Nom, QFN, 10 PIN

SIT3542ACA2C2301SY340.000001 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid145148652237
package instructionLCC10,.12X.2,50/40
Reach Compliance Codeunknown
Country Of OriginMalaysia, Taiwan, Thailand
YTEOL6.8
Other featuresENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT
maximum descent time0.46 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Number of terminals10
Nominal operating frequency340.000001 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
Oscillator typeLVDS
Output load100 OHM
Encapsulate equivalent codeLCC10,.12X.2,50/40
physical size5.0mm x 3.2mm x 0.9mm
longest rise time0.46 ns
Maximum supply voltage3.3 V
Minimum supply voltage2.7 V
Nominal supply voltage3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
SiT3542
340 to 725 MHz Endura™ Series I
2
C/SPI Programmable Oscillator
Features
Description
The
SiT3542
is a ruggedized, ultra-low jitter, user
programmable oscillator with a maximum acceleration
sensitivity of 0.1 ppb/g. SiT3542, designed for high reliability
applications, offers the system designer great flexibility and
functionality in the most demanding environments.
The device supports two in-system programming options
after powering up at a default, factory programmed startup
frequency:
0.1 ppb/g acceleration sensitivity for harsh environments
Programmable frequencies (factory or via I
2
C/SPI)
from 340.000001 MHz to 725 MHz
Digital frequency pulling (DCO) via I
2
C/SPI
Output frequency pulling with perfect pull linearity
13 programmable pull range options to
±3200
ppm
Frequency pull resolution as low as 5 ppt (0.005 ppb)
0.21 ps typical integrated phase jitter (12 kHz to 20 MHz)
Integrated LDO for on-chip power supply noise filtering
0.02 ps/mV PSNR
-40°C to 105°C operating temperature
LVPECL, LVDS, or HCSL outputs
Programmable LVPECL, LVDS Swing
LVDS Common Mode Voltage Control
RoHS and REACH compliant, Pb-free, Halogen-free
and Antimony-free
Any-frequency mode where the clock output can be re-
programmed to any frequency between 340 MHz and
725 MHz in 1 Hz steps
Digitally controlled oscillator (DCO) mode where the
clock output can be steered or pulled by up to
±3200
ppm with 5 to 94 ppt (parts per trillion) resolution.
A user specifies the device’s default start-up frequency in
the ordering code. User programming of the device is
achieved via I
2
C or SPI. Up to 16 I
2
C addresses can be
specified by the user either as a factory programmable
option or via hardware pins, enabling the device to share
the I
2
C with other I
2
C devices.
The SiT3542 utilizes SiTime’s unique DualMEMS™
temperature sensing and TurboCompensation™ technology
to deliver exceptional dynamic performance
Applications
Land Mobile Communications
Avionics
Airframe / Engine Management Control
Satellite Base Stations
Resistant to airflow and thermal shock
Resistant to shock and vibration
Superior power supply noise rejection
Block Diagram
Package Pinout
(10-Lead QFN, 5.0 x 3.2 mm)
O
IS
M
A/ K
SD C L
S
10
9
OE / NC
OE / NC
GND
1
8
VDD
OUT-
OUT+
2
7
3
4
5
6
A1 A0
/N /N
C/ C/
M SS
O
SI
Figure 1. SiT3542 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 14
for Pin Descriptions)
Rev 1.00
July 24, 2020
www.sitime.com
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