Pin Description and Physical Orientation...................................................................................................................................8
Power - Estimated.......................................................................................................................................................................9
Test Definitions .............................................................................................................................................................................16
Test Regions of Interest ............................................................................................................................................................16
Test Sub Regions of Interest.....................................................................................................................................................16
Maximum Ratings .....................................................................................................................................................................19
Maximum Voltage Ratings Between Pins ................................................................................................................................19
DC Bias Operating Conditions ..................................................................................................................................................20
AC Operating Conditions...........................................................................................................................................................21
Clock Line Capacitances .......................................................................................................................................................21
One Output Full Field ............................................................................................................................................................28
Two Outputs Full Field ..........................................................................................................................................................29
One Output Center Columns.................................................................................................................................................30
Two Outputs Center Columns...............................................................................................................................................31
One Output Center Rows.......................................................................................................................................................32
Two Outputs Center Rows.....................................................................................................................................................33
One Output Center Rows and Columns................................................................................................................................34
Two Outputs Center Rows and Columns..............................................................................................................................35
Vertical Clocks Phases 1 and 2 – Line Timing Detail...........................................................................................................39
Electronic Shutter – Integration Time Definition .................................................................................................................44
Fast Line Dump Timing .........................................................................................................................................................45
Example HCCD Clock Driver.....................................................................................................................................................46
Single Output Only.................................................................................................................................................................46
Selectable Single or Dual Output..........................................................................................................................................46
Storage and Handling ...................................................................................................................................................................47
Die to Package Alignment.........................................................................................................................................................49
Quality Assurance and Reliability.................................................................................................................................................53
Ordering Information ....................................................................................................................................................................54
Figure 3: Power ...............................................................................................................................................................................9
Figure 5: Monochrome with Microlens Quantum Efficiency .......................................................................................................14
Figure 6: Color with Microlens Quantum Efficiency ....................................................................................................................14
Figure 9: Test Sub Regions of Interest.........................................................................................................................................16
Figure 10: Overclock Regions of Interest.....................................................................................................................................16
Figure 18: Integration Time Definition .........................................................................................................................................44
Figure 19: Fast Line Dump Timing...............................................................................................................................................45
Figure 21: Die to Package Alignment...........................................................................................................................................49
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