PRELIMINARY
DS1500/DS1510
Y2KC Watchdog RTC with NV Control
www.dalsemi.com
FEATURES
BCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year
2100
Programmable Watchdog Timer and RTC
Alarm
Century register; Y2K Compliant RTC
Automatic battery backup and write
protection to external SRAM
+3.3 or +5V operation
Precision Power-On Reset
Power control circuitry supports system
power on from date/day/time alarm or key
closure
256 bytes user NV RAM
Auxiliary battery input
Accuracy of DS1510 is better than ±1
minute/month at 25
°
C
Day of week/Date alarm register
Battery voltage level indicator flags
Available as chip or standalone module with
embedded battery and crystal
Optional industrial temperature range -40
°
C
to +85
°
C (DS1500 only)
PIN ASSIGNMENT
ORDERING INFORMATION
DS1500XXX
blank commercial temp range
N
industrial temp range
blank 32-pin DIP
E
32-pin TSOP
Y
W
DS1510X
5V operation
3.3V operation
DIP Module
Y
W
5V
3.3V
Package Dimension Information can be found at:
http:\\www.Dalsemi.com/datasheets/mechdwg.html
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110100
DS1500/DS1510
PIN DESCRIPTION
V
CCI
A0-A4
DQ0-DQ7
CS
OE
WE
IRQ
PWR
RST
- Supply Voltage
- Address Inputs
- Data I/O
- RTC Chip Select Input
- RTC Output Enable Input
- RTC Write Enable Input
- Interrupt Output (open drain)
- Power-On Output (open drain)
- Reset Output (open drain)
KS
SQW
V
BAT
V
BAUX
CEI
CEO
V
CCO
X1, X2
GND
- Kickstart Input
- Square wave output
- Backup Battery Supply
- Auxiliary Battery Supply
- RAM Chip Enable Input
- RAM Chip Enable Output
- RAM Power Supply Output
- 32.768 kHz Crystal pins
- Ground
DESCRIPTION
The DS1500/DS1510 is a full function, year 2000 compliant, real-time clock/calendar (RTC) with an
alarm, watchdog timer, power-on reset, battery monitors, 256 bytes of on board non-volatile static RAM,
NV control for backing up an external SRAM, and a 32.768 kHz output. User access to all registers
within the DS1500/DS1510 is accomplished with a bytewide interface as shown in Figure 1. The RTC
registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD
format. Corrections for day of month and leap year are made automatically.
The RTC registers are double buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. When the crystal oscillator is turned on, the internal set of registers are
continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC
information is always maintained.
The DS1500/DS1510 contains its own power fail circuitry which automatically deselects the device when
the V
CCI
supply falls below a power fail trip point. This feature provides a high degree of data security
during unpredictable system operation brought on by low V
CCI
levels. An external SRAM can be made
nonvolatile by using the V
CCO
and
CEO
pins. Nonvolatile control of the external SRAM is analogous to
that of the real-time clock registers. When V
CCI
slews down during a power fail,
CEO
is driven to an
inactive level regardless of
CEI
. This write protection occurs when V
CCI
is less than the power fails trip
point.
The DS1500/DS1510 has interrupt (
IRQ
), power control (
PWR
), and reset (
RST
) outputs which can be
used to control CPU activity. The
IRQ
interrupt or
RST
outputs can be invoked as the result of a time of
day alarm, CPU watchdog alarm, or a kick start signal. The DS1500/1511 power control circuitry allows
the system to be powered on via an external stimulus, such as a keyboard or by a time and date (wake-up)
alarm. The
PWR
output pin can be triggered by one or either of these events, and can be used to turn on
an external power supply. The
PWR
pin is under software control, so that when a task is complete, the
system power can then be shut down. The DS1500/DS1510 power-on reset can be used to detect a
system power down or failure and hold the CPU in a safe reset state until normal power returns and
stabilizes; the
RST
output is used for this function.
The DS1500 is a clock/calendar chip with the features described above. An external crystal and battery
are the only components required to maintain time-of-day and memory status in the absence of power.
The DS1510 incorporates the DS1500 chip, a 32.768 kHz crystal, and a lithium battery in a complete,
self-contained timekeeping module. The entire unit is designed by Dallas Semiconductor to provide a
minimum of 10 years of timekeeping and data retention in the absence of V
CCI
is guaranteed.
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DS1500/DS1510
DS1500/DS1510 BLOCK DIAGRAM
Figure 1
V
CCI
DS1500/DS1510 RTC OPERATING MODES
Table 1
V
CCI
V
CCI
> V
PF
CS
OE
WE
V
SO
<V
CCI
<
V
PF
V
CCI
<
V
SO
< V
PF
V
IH
V
IL
V
IL
V
IL
X
X
X
X
V
IL
V
IH
X
X
X
V
IL
V
IH
V
IH
X
X
DQ0-DQ7
High-Z
D
IN
D
OUT
High-Z
High-Z
High-Z
A0-A4
X
A
IN
A
IN
A
IN
X
X
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
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DS1500/DS1510
RTC DATA READ MODE
The DS1500/DS1510 is in the read mode whenever
CS
(chip select) is low and
WE
(write enable) is high.
The device architecture allows ripple through access to any valid address location. Valid data will be
available at the DQ pins within t
AA
(Address Access) after the last address input is stable, providing that
CS
and
OE
access times are satisfied. If
CS
or
OE
access times are not met, valid data will be available at
the latter of chip enable access (t
CSA
) or at output enable access time (t
OEA
). The state of the data
input/output pins (DQ) is controlled by
CS
and
OE
. If the outputs are activated before t
AA
, the data lines
are driven to an intermediate state until t
AA
. If the address inputs are changed while
CS
and
OE
remain
valid, output data will remain valid for output data hold time (t
OH
) but will then go indeterminate until the
next address access. (See Table 1.)
RTC DATA WRITE MODE
The DS1500/DS1510 is in the write mode whenever
WE
and
CS
are in their active state. The start of a
write is referenced to the latter occurring transition of
WE
or
CS
. The addresses must be held valid
throughout the cycle.
CS
or
WE
must return inactive for a minimum of t
WR
prior to the initiation of a
subsequent read or write cycle. Data in must be valid t
DS
prior to the end of the write and remain valid for
t
DH
afterward. In a typical application, the
OE
signal will be high during a write cycle. However,
OE
can
be active provided that care is taken with the data bus to avoid bus contention. If
OE
is low prior to a
high to low transition on
WE
, the data bus can become active with read data defined by the address inputs.
A low transition on
WE
will then disable the outputs t
WEZ
after
WE
goes active. (See Table 1.)
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written and read only when V
CCI
is greater than V
PF
.
However, when V
CCI
falls below the power fail point V
PF
(point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. While in the data retention mode, all
inputs are ‘don’t cares’ and outputs go to a high-Z state with the exception of V
CCO
,
CEO
, and the possible
exception of
KS
,
PWR
, SQW, and
RST
. When V
CCI
falls below the greater of V
BAT
or V
BAUX
, device
power is switched from the V
CCI
pin to the greater of V
BAT
or V
BAUX
. RTC operation and external SRAM
data are maintained from the battery until V
CCI
is returned to nominal levels. (See Table 1.)
The 3.3 volt device is fully accessible and data can be written and read only when V
CCI
is greater than
V
PF
. However, when V
CCI
falls below V
PF
, access to the device is inhibited. If V
PF
is less than V
BAT
and
V
BAUX
, the device power is switched from V
CCI
to the greater of V
BAT
and V
BAUX
when V
CCI
drops below
V
PF
. If V
PF
is greater than V
BAT
and V
BAUX
, the device power is switched from V
CCI
to the greater of V
BAT
and V
BAUX
when V
CCI
drops below the greater of V
BAT
and V
BAUX
. RTC operation and external SRAM
data are maintained from the battery until V
CCI
is returned to nominal levels. (See Table 1.)
All control, data, and address signals must be no more than 0.3 volts above V
CCI
.
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DS1500/DS1510
AUXILIARY BATTERY
The V
BAUX
input is provided to supply power from an auxiliary battery for the DS1500/DS1510 kickstart
and SQW output features in the absence of V
CCI
. This power source must be available in order to use
these auxiliary features when no V
CCI
is applied to the device.
This auxiliary battery may be used as the primary backup power source for maintaining the clock/calendar
and external SRAM. This occurs if the V
BAT
pin is at a lower voltage than V
BAUX
. If the DS1500/DS1510
is to be backed-up using a single battery with the auxiliary features enabled, then V
BAUX
should be used
and connected to V
BAT
. If V
BAUX
is not to be used, it should be grounded.
POWER ON RESET
A temperature compensated comparator circuit monitors the level of V
CCI
. When V
CCI
falls to the power
fail trip point, the
RST
signal (open drain) is pulled low. When V
CCI
returns to nominal levels, the
RST
signal continues to be pulled low for a period of 40 ms to 200 ms. The power on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To increase the shelf life of a backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The
EOSC
bit is used
to control state of the oscillator, and must be set to a "0" for the oscillator to function.
READING THE CLOCK
When reading the clock and calendar data, it is recommended to halt updates to the external set of double
buffered RTC registers. This puts the external registers into a static state allowing data to be read without
register values changing during the read process. Normal updates to the internal registers continue while
in this state. External updates are halted when a ”0” is written into the read (TE) bit of Control register B
(0 Fh). As long as a “0” remains in the Control register B (TE) bit, updating is halted. After a halt is
issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt
command was issued. Normal updates to the external set of registers will resume within 1 second after
the (TE) bit is set to a “1”.
SETTING THE CLOCK
It is also recommended to halt updates to the external set of double buffered RTC registers when writing
to the clock. The (TE) bit should be used as described above before loading the RTC registers with the
desired RTC count (day, date, and time) in 24-hour BCD format. Setting the (TE) bit to a “1” will
transfer the values written to the internal RTC registers and allows normal operation to resume.
CLOCK ACCURACY
A standard 32.768 kHz quartz crystal should be directly connected to the DS1500 X1 and X2 oscillator
pins. The crystal selected for use should have a specified load capacitance (C
L
) of either 6 pF or 12.5 pF,
and the Crystal Select (CS) bit set accordingly. For more information on crystal selection and crystal
layout considerations, please consult Application Note 58, “Crystal Considerations with Dallas Real Time
Clocks.” The DS1500 can also be driven by an external 32.768 kHz oscillator. In order to achieve low
power operation when using an external oscillator, it may be necessary to connect the X1 pin to the
external oscillator signal through a series connection consisting of a resistor and a capacitor. A typical
configuration consists of a 1.0Meg resistor in series with a 100 pF ceramic capacitor. When using an
external oscillator the X2 pin must be left open. Accuracy of DS1510 is better than ±1 min./month at
25
°
C.
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