75A, 600V MAGNUM MOTOR DRIVES
FEATURES
• 600 Vdc Drive for 270 Vdc Motors
• 75 Amps @25°C, 50 Amps @85°C
• Operates with Brushless, Brush and
Induction Motors
• Input to Output Ground Isolation with
Floating Output Stage
• Short Circuit Protection
SLEEP MODE
POWER
SUPPLY
VCC
VCC RTN
UPPER
I
S
O
L
A
T
I
O
N
B
A
R
R
I
E
R
POWER
SUPPLY
VBUS+
HIGH
DRIVE
SC FAULT
DISABLE/RESET
AUTO RESET
LOWER
GATE
DRIVE
AND
FAULT
CONTROL
OUTPUT
LOW
DRIVE
VBUS-
FIGURE 1A. PW-83075P6 BLOCK DIAGRAM
• Trapezoidal or Sinusoidal Compatible
• DSP/Microprocessor Compatible
• PW-83075P6 - Half-Bridge Drive
• PW-84075P6 - Half-Bridge Drive with Current
Sense
• PW-85075P6 - Half-Bridge Drive with
Regenerative Clamp
SLEEP MODE
POWER
SUPPLY
I
S
O
L
A
T
I
O
N
B
A
R
R
I
E
R
LOW
DRIVE
POWER
SUPPLY
VCC
VCC RTN
VBUS+
HIGH
DRIVE
UPPER
SC FAULT
DISABLE/RESET
AUTO RESET
LOWER
VDD
VDD RTN
I_VOUT
OC FAULT
VREF
I_ABSVAL
GATE
DRIVE
AND
FAULT
CONTROL
OUTPUT
VBUS-
RSENSE+
CURRENT
AMP
CURRENT
AMP
R
SENSE
DESCRIPTION
The PW-83075P6, PW-84075P6 and PW-85075P6 are half-
bridge drive modules which contain isolated switch drivers, a
pair of solid state switches, an isolated power supply, current
sensing feedback (PW-84075P6 only) and a regenerative clamp
protection circuit (PW-85075P6 only). The three modules can
be used, in any combination, to create drives for brush, brush-
less DC motors or AC induction motors. The logic inputs and
current sense signal are compatible with DSP/microprocessors
and/or FPGA/ASIC circuits used to control the motor drives.
These modular drives are capable of operating from either
±135Vdc or 270Vdc power source that is totally isolated from
the logic input signals. The modules are fault tolerant from out-
put shorts, loss of any or all power supplies and power supply
sequencing.
APPLICATIONS
The high reliability and flexibility of these drives make them suit-
able for Military and Aerospace applications. Among the many
applications are: actuator systems for primary and secondary
flight controls on aircraft; fan and compressor motor drives for
environmental conditioning; pump motors for fuel and hydraulic
fluid; antenna and radar positioning; and thrust vector position
control of missiles, drones, and RPV’s.
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June 13, 2000 Data Device Corporation
RSENSE-
FIGURE 1B. PW-84075P6 BLOCK DIAGRAM
REGEN STATUS
VBUS+
OV ADJ
REGEN BUS-
SLEEP MODE
POWER
SUPPLY
POWER
SUPPLY
OV
AMP
REGEN
LOW
VCC
VCC RTN
UPPER
SC FAULT
I
S
O
L
A
T
I
O
N
B
A
R
R
I
E
R
REGEN
BUS-
VBUS+
HIGH
DRIVE
DISABLE/RESET
AUTO RESET
LOWER
GATE
DRIVE
AND
FAULT
CONTROL
OUTPUT
LOW
DRIVE
VBUS-
FIGURE 1C. PW-85075P6 BLOCK DIAGRAM
TABLE 1. PW-8X075P6 ABSOLUTE MAXIMUM RATINGS
(TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
Drive Supply Voltage
Logic Power-In Supply Voltage
Input Logic Voltage
Continuous Output Current
Peak Output Current (10 ms)
Storage Temperature Range
Intermittent Case Operating Temperature
Continuous Case Operating Temperature
Junction Temperature, Power Devices
Junction Temperature, Other Components
Ground Isolation Voltage (Note 2)
SYMBOL
VBUS+ to VBUS-
VCC
UPPER, LOWER, DISABLE/RESET,
SLEEPMODE, AUTO RESET
I
O
I
PEAK
Tcs
T
CI
Tc
Tj
T
J
V
ISO
VALUE
600
5.5
5.5
75
150
-65 to +125
-55 to +125
-55 to +100
+150
+125
2500
UNITS
Vdc
Vdc
Vdc
A
A
°C
°C
°C
°C
°C
Vdc
TABLE 2. PW-8X075P6 SPECIFICATIONS
(TC = +25°C, VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED)
PARAMETER
OUTPUT STAGE
Drive Supply Voltage (motor)
Output Switch Transistors (each)
Continuous Current Drive
Peak Current
Short Circuit Trip Current (note 1)
Output Voltage Drop (IGBT)
FLYBACK DIODE
Instant Forward Voltage
Reverse Recovery Time @ T
j
= +125° C
Reverse recovery Peak Current
Reverse Leakage Current @ T
j
= +25° C
Reverse Leakage Current @T
j
= +125° C
OUTPUT SWITCHING
CHARACTERISTICS (See FIGURE 5)
Turn-on Propagation Delay
Turn-off Propagation Delay
Disable Propagation Delay
Turn-on Rise Time
Turn-off Fall Time
Sleep_Mode Delay
Output Switching Frequency
POWER AND LOGIC SUPPLY
(PW83075P6 ONLY)
Voltage
Current
Control Inputs
UPPER, LOWER, DISABLE/RESET
AUTO RESET
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
UPPER, LOWER
High Level Input Current
Low Level Input Current
RESET/DISABLE
High Level Input Current
Low Level Input Current
AUTO_RESET
High Level Input Current
Low Level Input Current
SLEEP_MODE
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
SYMBOL
VBUS+
TO
VBUS-
I
O
I
PEAK
I
SC
V
F
T
rr
Irm
TEST CONDITIONS
Unipolar/Bipolar
+25°C case
+85°C case
+85°C case,≤15
ms
≤5
µs
I
O
= 50A
I
O
= 50A
I
O
= 50A
di/dt = 480A/µs
I
F
= 50A (90 °C)
VBUS = 480Vdc
VBUS = 480Vdc
MIN
0
TYP
270
MAX
600
75
50
100
400
2.6
1.9
33
325
17
UNITS
Vdc
A
A
A
A
Vdc
Vdc
ns
A
µA
mA
200
V
CE(SAT)
350
2.2
1.7
175
19
30
I
r
I
r
td(on)
td(off)
t
s
d
tr
tf
tsleepu
fPWM
390
740
100
100
140
3.7
0
470
840
200
200
35
ns
ns
µs
ns
ns
ms
KHz
VCC
ICC
4.5
f = 25 KHz
5.0
110
5.5
Vdc
mA
VCC = 4.5V
VIH
VIL
VHYST
IIH
IIL
IIH
IIL
IIH
IIL
VIH
VIL
IIH
IIL
Vin = VCC
Vin = 0V
Vin = VCC
Vin = 0V
Vin = VCC
Vin = 0V
VCC = 4.5V
Vin = VCC
Vin = 0V
1.55
0.9
0.4
22
0
22
1.3
2.4
0.8
0.1
0.4
0.5
2.5
1.6
0.9
23
0.1
0
23
0
1.4
3.15
2.45
2.1
24
100
24
1.5
Vdc
Vdc
Vdc
µA
nA
µA
µA
µA
mA
Vdc
Vdc
µA
mA
2
June 13, 2000 Data Device Corporation
TABLE 2. PW-8X075P6 SPECIFICATIONS
(TC = +25°C, VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED)
PARAMETER
UPPER-LOWER DEADTIME
AUTO_RESET Delay to output off
AUTO_RESET Delay to output enabled
RESET pulsewidth to clear SC_FAULT
Cycle time between AUTO_RESET retries
CONTROL OUTPUTS
SC_FAULT
High Level Current
Low Level Current
THERMAL
Maximum Thermal Resistance - IGBT
- Diode
Junction Temperature Range
Case Operating Temperature
Case Storage Temperature
MECHANICAL
Maximum Lead Soldering Temp
Mounting Torque
Weight
Ts
+250
3
TBD
°C
in-lbs
oz (gr)
θjc
θjc
Tj
Tc
Tcs
Each Output Switch
-55
-55
-65
0.5
0.8
0.55
+150
+100
+125
°C/W
°C/W
°C
°C
°C
SYMBOL
tdead
tdoff.auto
tdon.auto
tpw.reset
tcycle.auto
TEST
CONDITION
MIN
1.0
202
3.0
100
40
100
TYP
MAX
UNITS
µs
ms
ms
ns
ms
ISCFLTH
ISCFLTL
Vo = VCC
Vo = 0.4V
22
5
23
10
24
µA
mA
Notes: 1. VBUS+ to VBUS- must be
≥
10V (during short circuit) for short circuit protection to operate.
2. From VCC RTN to VBUS+, VBUS-, OUTPUT, REGEN LOW, RSENSE+, RSENSE-.
TABLE 3. PW-84075P6 SPECIFICATIONS
(TC= +25°C VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED)
PARAMETER
Current Amplifier
I_Vout Trasnfer Ratio
I_Vout Gain Error
I_Vout Offset
I_Vout Offset Drift
I_Vout Gain %
I_Vout Offset %
I_Vout Offset % Drift
I_VABS Gain
I_VABS Gain Error
I_VABS Offset
I_VABS Offset Drift
I_VABS Gain %
I_VABS Offset %
I_VABS Offset % Drift
Delay Time
Bandwidth
Linear Range
OC_FAULT trip level
Reference voltage input current
OC_FAULT
High Level Input Current
Low Level Input Current
Power and Logic Supply
Voltage
Logic Supply Current
Current Amplifier Supply Current
SYMBOL
Gvout
Evout
Vos
TCVos
Gvout%
Vos%Vref
TCVos%
Gvabs
Evabs
Vosabs
TCVosabs
Gvout%
Vosabs% Vref
TCVosabs%
tdelay
fBW
Irange
IOC
Ivref
IOCFLTH
IOCFLTL
VCC, VDD
ICC
IDD
TEST
CONDITION
Vref = 5.0V
Vref = 5.0V
Vref = 5.0V
0A = Vref/2
0A = 0V
Vref = 5.0V
Vref = 5.0V
0A = 0V
-8
-131
-90
1.19
-2.6
-18
20
±75
9
30
±50
±85
0.26
0.2
4
4.5
Gate Off / SLEEP MODE
25Khz Gate Pulsing
8
5
11
136
10
5.5
200
20
2.6
22
20
±95
1
15
-6
-30
-90
0.595
-0.6
-18
59.52
8
131
110
0.6
22
MIN
TYP
29.76
6
30
110
MAX
UNITS
mV/A
%
mV
ppm/°C
%Vref/A
%Vref
ppm/Vref/°C
mV/A
%
mV
ppm/°C
%Vref/A
%Vref
ppm/Vref/°C
µs
kHz
A
A
mA
uA
mA
V
mA
mA
mA
Vo = VDD
Vo = 0.8V
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June 13, 2000 Data Device Corporation
TABLE 4. PW-85075P6 SPECIFICATIONS
(TC = +25°C, VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED)
PARAMETER
Over Voltage Transistor
Continuous Current Drive
Peak Current
Output Voltage Drop (IGBT)
Reverse Leakage @ T
J
= +25°C
Reverse Leakage @ T
J
= +125°C
Over Voltage flyback Diode
Reverse Leakage @ Tc = +25°C
Reverse Leakage @ Tc = +125°C
Over Voltage Trip
Trip Level Hysteresis
Power and Logic Supply
Voltage
Current
REGEN STATUS
(ref. to REGEN BUS-)
High Level Output Voltage
Low Level Output Voltage
Output resistance
Vtrip rise to status ON Delay
Vtrip fall status OFF Delay
THERMAL
Maximum Thermal Resistance
SYMBOL
Io
I
PEAK
V
CE
(
SAT
)
Ir
Ir
Ir
Ir
Vtrip
Vhyst
VCC
ICC
TEST
CONDITION
+25°C Case
+85°C Case
+85°C Case, 15 ms
2.0
600 Vdc
600 Vdc
480 Vdc
480 Vdc
no external adjustments
20
1
400
40
5
11
137
15
0.2
4.75
36
48
0.7
MIN
TYP
MAX
35
30
60
3.0
250
1.0
50
7
430
45
5.5
250
15.6
0.4
4.8
UNITS
A
A
A
Vdc
µA
mA
µA
mA
Vdc
Vdc
V
mA
mA
Vdc
Vdc
KΩ
µs
µs
°C/W
370
35
4.5
Gate Off/ Sleep Mode
25Khz Gate Pulsing
I0 = 0
I0 = 0
13.8
4.2
VOHstatus
VOLstatus
Rstatus
tdon.status
tdoff.status
θjc
Over Voltage Switch
0.85
INTRODUCTION
The PW-8X075P6 is a universal modular half-bridge motor drive
intended for use with brush, brushless DC and AC induction
motors in aerospace applications.
The isolation barrier, which separates the power and control
stage, attenuates the ground noise generated from high speed,
high power switching. All signals from the control to the power
sections are isolated from power and ground of the other section.
This eliminates false triggering of the input signals and the need
for creative grounding schemes. The isolation barrier also allows
the user to operate the output stage from either unipolar or bipo-
lar power supplies without level shifting the input signals.
A built in power supply located in the control stage provides
power to all electronics in the power stage. This eliminates the
need for refresh cycles or external power supplies for the gate
drive circuitry and allows switching duty cycles from 0 - 100%.
PW-84075P6 provides current sensing of either motor current or
DC bus current. This current signal can be used as a feedback
signal in a servo drive to create a torque loop.
The output power transistors are protected from a short circuit or
overvoltage condition (requires PW-85075P6) applied to the out-
put pins. When a short circuit condition is detected, the output
transistor is shut down and a flag is active indicating a short has
occurred. When an overvoltage condition is detected, the over-
voltage switch is enabled and a external load dump resistor is
connected across the high voltage bus. A status flag is active
indicating an overvoltage condition has occurred.
FUNCTIONAL AND
PIN
DESCRIPTIONS: (FOR PW-83075P6,
PW-84075P6 AND PW-85075P6 UNLESS NOTED)
URE 2, between UPPER and LOWER inputs is necessary to pre-
vent output cross conduction.
SC FAULT
The SC FAULT output signal indicates when the output of the
motor drive has experienced a short circuit condition. The signal
is normally at a logic high (H). A transition to a logic low (L) will
occur once a short circuit condition is detected. See
SHORT CIR-
CUIT OPERATION
for more detail.
DISABLE / RESET
The DISABLE/RESET control input is CMOS Schmitt-trigger
input and enables (reset) or disables the controller. When the DIS-
ABLE/RESET input receives a logic low (L) pulse for at least 0.1
µs, the SC FAULT output will go high (H) indicating that the inter-
nal circuitry has been enabled or reset. To reset the motor drive,
a logic low (L) must be presented to the DISABLE/RESET inputs
when the AUTO RESET is inactive or at a logic high (H).
AUTO RESET
When the AUTO RESET is tied to SC FAULT, the protection circuit
will reset automatically after the short circuit fault has occurred,
enabling the output to respond to the input commands. See
SHORT CIRCUIT OPERATION
for more detail.
SHORT CIRCUIT OPERATION
The PW-8X075P6 outputs are completely short-circuit-protected
from either a hard or soft short (required PW-84075 and some
external circuit) to the VBUS+ or VBUS- lines. Each output tran-
sistor is individually short-circuit (hard) protected by circuitry that
detects the desaturation voltage for that transistor during a short
condition. Once a hard short circuit condition is detected, the
active output transistors are shutdown. If the AUTO RESET is
tied to SC FAULT, the circuit will auto reset, remove the short cir-
cuit flag, and reactivate the output transistor within 40 to 100ms.
4
UPPER, LOWER
The UPPER and LOWER are CMOS Schmitt-trigger inputs and
control the gate drives of the output transistors. Each input is elec-
trically isolated from the output. A deadband, as shown in FIG-
June 13, 2000 Data Device Corporation
power supply is shut down (SLEEP MODE input high), the voltage
at I_VOUT will indicate 0V.
50%
UPPER
50%
VREF (APPLIES TO PW-84075P6 ONLY)
A voltage reference from an external source is connected to the
VREF pin to set the output voltage scale for I_VOUT.
50%
LOWER
0.6 µs Min.
50%
RSENSE+, RSENSE- (APPLIES TO PW-84075P6 ONLY)
0.6 µs Min.
FIGURE 2. PW-8X075P6 DEAD BAND REQUIREMENT
If the short is still present, the circuit will repeat the shut down
and auto reset until the short is clear. The users can use the
DISABLE/RESET (H) to shut down the gate drivers if a short per-
sists. The AUTO RESET is inactive when it presented a logic
high (H). Protecting against a soft-short requires a PW-84075
(current sensing) and external circuitry. When a soft-short
occurs, the external circuit can activate the SLEEPMODE (H)
and shut down the gate drivers.
These pins are across RSENSE and can be connected in series
with the output, VBUS+ or VBUS- to measure current. The inter-
nal connections to RSENSE are Kelvin to minimize errors.
However, these pins can be connected absolutely anywhere with-
in the isolation restrictions on the pins (600V to power pins, 2500V
to logic pins).
I _ABSVAL (APPLIES TO PW-84075P6 ONLY)
The I_
ABSVAL
output voltage is the absolute value of the I_VOUT
voltage signal. The scale is 0 to VREF for +/- current in RSENSE.
OC FAULT (APPLIES TO PW-84075P6 ONLY)
The OC FAULT output is an open drain output which indicates that
current flowing through RSENSE has exceeded the overcurrent
threshold. Once the fault threshold is exceeded, the output tran-
sitions from open drain to low within 6 µs.
SLEEP MODE
The SLEEP MODE input turns the internal power supply on or off.
A logic high (H) on the SLEEP MODE input disables the internal
power supply, disabling the motor drive output. No damage will
occur to the motor drive during turn on or turn off of the power sup-
ply. Additionally, no special power up sequence is required. A
logic low (L) turns the power supply on and allows the motor drive
to operate normally.
REGEN STATUS (APPLIES TO PW-85075P6 ONLY)
The REGEN STATUS pin is referenced to REGEN BUS-. It indi-
cates the state of the regen clamp switch, H = on, L = off. An
external opto-isolator input can be connected between REGEN
STATUS and REGEN BUS- to translate this status to logic circuits,
if desired.
VCC, VCC RTN
The VCC and VCC RTN are power connections that supply input
power to the internal power supply, the gate drive and fault con-
trol circuits.
OV ADJ (APPLIES TO PW-85075P6 ONLY)
The PW-85075P6 is internally set for a trip voltage of 400V. To set
a different trip voltage, an external resistor is connected from the
OV ADJ pin to either REGEN BUS- or VBUS+ pins (See FIG-
URES 4A and 4B). These pins are available on the control pins.
This resistor should be selected for the voltage, Vmax, for the
overvoltage switch to turn on.
75
70
VBUS+, VBUS-
VBUS+ and VBUS- are the high voltage power connections to the
output stage. The high voltage can be either unipolar, +V and
ground or bipolar, +/- V. External capacitor filtering will be
required. See DDC applications note AN/H-6.
OUTPUT
Output Phase Current, IAVG (amps)
The output connects to one input of the motor and applies VBUS+,
VBUS-, or high impedance to the motor based on the state of the
control inputs. It is capable of sourcing or sinking up to 75 Amps,
and the output can withstand a short circuit to VBUS+ or VBUS-
without any damage by automatically turning itself off (Zstate).
65
60
55
50
45
40
35
30
25
20
15
10
5
0
25
35
45
55
65
75
85
95
105
115
125
5 kHz
VDD, VDD RTN (APPLIES TO THE PW-84075P6 ONLY)
The VDD and VDD RTN supply input power to the current ampli-
fier.
I_VOUT (APPLIES TO PW-84075P6 ONLY)
The voltage on the I_VOUT pin represents current passing
through RSENSE in the direction shown in the block diagram.This
I_VOUT voltage is scaled by the input voltage at VREF, where
I_VOUT = (VREF/2) + (VREF/150) * I_RSENSE
where, I_RSENSE is current through RSENSE
I_VOUT is electrically isolated from the output stage. When the
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June 13, 2000 Data Device Corporation
VBUS+ = 270 Vdc
Duty Cycle = 50%
Tj(max) = 150°C
10 kHz
15 kHz
20 kHz
25 kHz
35 kHz
Maximum Operating Case Temperature, Tc °C
FIGURE 3. PW-8X075P6 OUTPUT PHASE CURRENT
VS. MAXIMUM OPERATING CASE TEMPERATURE
FPGA/CPLD
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