P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z86E30/E31/E40
Z8 4K OTP M
ICROCONTROLLER
FEATURES
Device
Z86E30
Z86E31
Z86E40
ROM
(KB)
4
2
4
RAM*
(Bytes)
237
125
236
I/O
Lines
24
24
32
Speed
(MHz)
16
16
16
s
1
Note:
*General-Purpose
s
s
s
Programmable OTP Options:
RC Oscillator
EPROM Protect
Auto Latch Disable
Permanently Enabled WDT
Crystal Oscillator Feedback Resistor Disable
RAM Protect
Low-Power Consumption: 60 mW
Fast Instruction Pointer: 0.75
µ
s
Two Standby Modes: STOP and HALT
Digital Inputs CMOS Levels, Schmitt-Triggered
Software Programmable Low EMI Mode
Two Programmable 8-Bit Counter/Timers Each
with a 6-Bit Programmable Prescaler
Six Vectored, Priority Interrupts from Six
Different Sources
Two Comparators
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
Standard Temperature (V
CC
= 3.5V to 5.5V)
Extended Temperature (V
CC
= 4.5V to 5.5V)
Available Packages:
28-Pin DIP/SOIC/PLCC OTP (Z86E30/31 only)
40-Pin DIP OTP (Z86E40 only)
PLCC/LQFP OTP (Z86E40 only)
44-Pin PLCC/QFP OTP (Z86E40 only)
Software Enabled Watch-Dog Timer (WDT)
Push-Pull/Open-Drain Programmable on
Port 0, Port 1, and Port 2
24/32 Input/Output Lines
s
s
s
s
s
s
s
s
s
s
s
s
s
Auto Latches
s
Auto Power-On Reset (POR)
GENERAL DESCRIPTION
The Z86E30/E31/E40 8-Bit One-Time Programmable
(OTP) Microcontrollers are members of Zilog's single-chip
Z8
®
MCU family featuring enhanced wake-up circuitry,
programmable Watch-Dog Timers, Low Noise EMI op-
tions, and easy hardware/software system expansion ca-
pability.
Four basic address spaces support a wide range of mem-
ory configurations. The designer has access to three addi-
tional control registers that allow easy access to register
mapped peripheral and I/O circuits.
DS97Z8X0502
For applications demanding powerful I/O capabilities, the
Z86E30/E31 have 24 pins, and the Z86E40 has 32 pins of
dedicated input and output. These lines are grouped into
four ports, eight lines per port, and are configurable under
software control to provide timing, status signals, and par-
allel I/O with or without handshake, and address/data bus
for interfacing external memory.
Notes:
All signals with a preceding front slash, “/”, are
active Low. For example, B/W (WORD is active Low); B/W
(BYTE is active Low, only).
1
PRELIMINARY
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