FT7C185A-20LMB
8K X 8 CMOS SRAM
x
Features
High-speed address/chip select access time
Mil:20/25/35/45/55/70/85/100(Max)
MB=Mil-Std-883 Method 5004
Low power consumption
Produced with advanced CMOS high-performance
technology
Inputs and outputs directly TTL-compatible
Three-state outputs
Available in 28-pin D=CERDIP and L= LCC
Description
The FT7C185 is a 65,536 bit high-speed static RAM organized as 8K
x 8. It is fabricated using high-performance, high-reliability CMOS
technology.
Address access times as fast as 15ns are available and the circuit
offers a reduced power standby mode. When
CS
1
goes HIGH or CS
2
goes LOW, the circuit will automatically go to, and remain in, a low-
power stand by mode. All inputs and outputs of the FT7C185 are TTL-
compatible and operation is from a single 5V supply, simplifying
system designs. Fully static asynchronous circuitry is used,
requiring no clocks or refreshing for operation.
The FT7C185 is packaged in a 28-
pin 600 mil CERDIP and a 32-pin ceramic LCC.
x
x
x
x
x
Functional Block Diagram
A
0
V
CC
ADDRESS
DECODER
65,536 BIT
MEMORY ARRAY
GND
A
12
0
7
I/O
0
I/O CONTROL
I/O
7
CS
1
CS
2
OE
WE
CONTROL
LOGIC
FT7C185A-20LMB
8K X 8 CMOS SRAM
Pin Configurations
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Absolute Maximum Ratings
(1)
V
CC
WE
CS
2
A
8
A
9
A
11
OE
A
10
CS
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
,
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com'l.
-0.5 to +7.0
Mil.
-0.5 to +7.0
Unit
V
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
-55 to +125
-55 to +125
1.0
50
-55 to +125
-65 to +135
-65 to +150
1.0
50
o
C
C
C
o
o
W
mA
Top View
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
Pin Descriptions
Name
A
0
- A
12
I/O
0
- I/O
7
CS
1
CS
2
WE
OE
GND
V
CC
Description
Address
Data Input/Output
Chip Select
Chip Select
Write Enable
Output Enable
Ground
Power
Truth Table
(1,2,3)
WE
X
X
X
X
H
H
L
CS
1
H
X
V
HC
X
L
L
L
CS
2
X
L
V
HC
or
V
LC
V
LC
H
H
H
OE
X
X
X
X
H
L
X
I/O
High-Z
High-Z
High-Z
High-Z
High-Z
DATA
OUT
DATA
IN
Function
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
Deselected - Standby (I
SB1
)
Output Disabled
Read Data
Write Data
NOTES:
1. CS
2
will power-down
CS
1
, but
CS
1
will not power-down CS
2
.
2. H = V
IH
, L = V
IL
, X = don't care.
3. V
LC
= 0.2V, V
HC
= V
CC
- 0.2V
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input HIGH Voltage
Input LOW Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
V
CC
+ 0.5
0.8
Unit
V
V
Recommended Operating
Temperature and Supply Voltage
Grade
Military
Temperature
-55
O
C to +125
O
C
-40
O
C to +85
O
C
0
O
C to +70
O
C
GND
0V
0V
0V
Vcc
5V ± 10%
5V ± 10%
5V ± 10%
V
Industrial
V
Commercial
____
NOTE:
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
FT7C185A-20LMB
8K X 8 CMOS SRAM
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
DC Electrical Characteristics
(1)
(V
CC
= 5.0V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
15
20
Com'l.
100
90
170
150
20
3
15
0.2
Mil.
110
100
180
160
20
5
20
1
Com'l.
90
80
170
150
20
3
15
0.2
25
Ind.
90
80
170
150
20
3
15
0.2
Mil.
110
100
180
160
20
5
20
1
mA
mA
mA
Unit
mA
Symbol
I
CC1
Parameter
Operating Power Supply Current
CS
1
= V
IL
, CS
2
= V
IH
, Outputs Open
V
CC
= Max., f
=
0
(2)
Dynamic Operating Current
CS
1
= V
IL
, CS
2
= V
IH
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current
(TTL Level),
CS
1
> V
IH
, CS
2
< V
IL
,
Outputs Open, V
CC
= Max., f = f
MAX
(2)
Full Standby Power Supply Current
(CMOS Level), f = 0
(2)
, V
CC
= Max.
1.
CS
1
> V
HC
and CS
2
> V
HC
, or
2. CS
2
< V
LC
Power
S
L
S
L
S
L
S
L
Com'l.
110
100
180
150
20
3
15
0.2
I
CC2
I
SB
I
SB1
35
Symbol
I
CC1
Parameter
Operating Power Supply Current
CS
1
= V
IL
, CS
2
= V
IH
, Outputs Open
V
CC
= Max., f
=
0
(2)
Dynamic Operating Current
CS
1
= V
IL
, CS
2
= V
IH
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current
(TTL Level),
CS
1
> V
IH
, CS
2
< V
IL
,
Outputs Open, V
CC
= Max., f = f
MAX
(2)
Power Com'l.
S
000 9 9000
8
S
L
S
L
150
130
20
3
15
1
90
9
Ind.
90
99
150
130
20
3
15
160
140
20
5
20
Mil.
100
45
Mil.
100
55
Mil.
100
70
Mil.
100
85/100
Mil.
100
0
L
8
mA
Unit
mA
I
CC2
160
130
20
5
20
1
160
125
20
5
20
1
160
120
20
5
20
1
160
120
20
5
20
1
I
SB
mA
I
SB1
Full Standby Power Supply Current
S
(CMOS Level), f = 0
(2)
, V
CC
= Max.
1.
CS
1
> V
HC
and CS
2
> V
HC
, or
L 0 . 0.
2
2
2. CS
2
< V
LC
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
FT7C185A-20LMB
8K X 8 CMOS SRAM
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
V
CC
= Max.,
V
IN =
GND to V
CC
V
CC
= Max.,
CS
1
= V
IH
,
V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OL
= 10mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
MIL.
COM'L. & IND
MIL.
COM'L. & IND
Min.
____
____
Max.
10
5
10
5
0.4
0.5
____
Min.
____
____
Max.
5
2
5
2
0.4
0.5
____
Unit
µA
µA
V
____
____
____
____
____
____
____
____
2.4
2.4
V
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
5V
480Ω
DATA
OUT
255Ω
30pF*
,
5V
480Ω
DATA
OUT
255Ω
5pF*
,
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ1,
t
CLZ2
, t
OLZ
, t
CHZ1,
t
CHZ2
, t
OHZ
, t
OW
, and t
WHZ
)
*Includes scope and jig capacitances
FT7C185A-20LMB
8K X 8 CMOS SRAM
AC Electrical Characteristics
(V
CC
= 5.0V ± 10%, All Temperature Ranges)
15
(1)
Symbol
Parameter
Min.
Max.
Min.
20
(2)
Max.
Min.
25
Max.
Min.
35
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS1
(3)
t
ACS2
(3)
t
CLZ1,2
(4)
t
OE
t
OLZ
(4)
t
CHZ1,2
(4)
t
OHZ
(4)
t
OH
t
PU
(4)
t
PD
(4)
Read Cycle Time
Address Access Time
Chip Select-1 Access Time
Chip Select-2 Access Time
Chip Select-1, 2 to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select-1,2 to Output in High-Z
Output Disab le to Output in High-Z
Output Hold from Address Change
Chip Sele ct to Power Up Time
Chip Deselect to Power Down Time
15
____
____
20
____
____
25
____
____
35
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
20
____
19
20
25
____
25
25
30
____
35
35
40
____
____
____
____
____
____
____
____
____
5
____
5
____
5
____
5
____
7
____
8
____
12
____
18
____
0
____
0
____
0
____
0
____
8
7
____
9
8
____
13
10
____
15
15
____
____
____
____
____
5
0
____
5
0
____
5
0
____
5
0
____
____
____
____
____
15
20
25
35
Write Cycle
t
WC
t
CW1,2
t
AW
t
AS
t
WP
t
WR1
t
WR2
t
WHZ
(4)
t
DW
t
DH1
t
DH2
t
OW
(4)
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time (CS
1
,
WE)
Write Recovery Time (CS
2
)
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time (CS
1
,
WE)
Data Hold from Write Time (CS
2
)
Output Active from End-of-Write
15
14
14
0
14
0
5
____
____
____
20
15
15
0
15
0
5
____
____
____
25
18
18
0
21
0
5
____
____
____
35
25
25
0
25
0
5
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
6
____
____
8
____
____
10
____
____
14
____
____
8
0
5
4
10
0
5
4
13
0
5
4
15
0
5
4
____
____
____
____
____
____
____
____
NOTES:
1. 0° to +70°C temperature range only.
2. 0° to +70°C and –55°C to +125°C temperature ranges only.
3. Both chip selects must be active for the device to be selected.
4. This parameter is guaranteed by device characterization, but is not production tested.
京公网安备 11010802033920号
EEWORLD
