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Datasheet> All Categories > storage> storage> LY625128LN-55SLE
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LY625128LN-55SLE

Description
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32,
Categorystorage    storage   
File Size275KB，16 Pages
ManufacturerLyontek
Websitehttp://www.lyontek.com.tw/index.html
Download Datasheet Parametric View All

LY625128LN-55SLE Overview

Standard SRAM, 512KX8, 55ns, CMOS, PDSO32,

LY625128LN-55SLE Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid107898724
package instructionTSSOP, TSSOP32,.8,20
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time55 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G32
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature80 °C
Minimum operating temperature-20 °C
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP32,.8,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.000023 A
Minimum standby current2 V
Maximum slew rate0.06 mA
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL EXTENDED
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL

LY625128LN-55SLE Preview

®
LY625128
Rev. 2.0
512K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Rev. 1.5
Rev. 2.0
Description
Initial Issue
Revised I
SB1
/I
DR
Revised Test Condition of I
CC
Added -45ns Spec.
Added P-DIP PKG
Revised Test Condition of I
SB1
/I
DR
Adding PKG type : 44 TSOP-II
Adding SL Spec.
Revised
ABSOLUTE MAXIMUN RATINGS
Issue Date
Jul.19.2005
Oct.31.2005
Sep.20.2006
Jan.12.2007
May.14.2007
Jun.4.2007
Jul.11.2007
40 Hsuch-Fu Rd., Hsinchu, Taiwan.
TEL: 886-3-5165511
FAX: 886-3-5165522
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
0
®
LY625128
Rev. 2.0
512K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The LY625128 is a 4,194,304-bit low power CMOS
static random access memory organized as 524,288
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The LY625128 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The LY625128 operates from a single power
supply of 4.5V ~ 5.5V and all inputs and outputs are
fully TTL compatible
FEATURES
Fast access time : 35/45/55/70ns
Low power consumption:
Operating current : 50/45/40/30mA (TYP.)
Standby current : 5μA (TYP.)
Single 4.5V ~ 5.5V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage : 2.0V (MIN.)
Lead free and green package available
Package : 32-pin 450 mil SOP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
32-pin 600 mil P-DIP
44-pin 400 mil TSOP-II
PRODUCT FAMILY
Product
Family
LY625128(SL)
LY625128(SLE)
LY625128(LL)
LY625128(LLE)
LY625128(LLI)
Operating
Temperature
0 ~ 70℃
-20 ~ 80℃
0 ~ 70℃
-20 ~ 80℃
-40 ~ 85℃
Vcc Range
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
Speed
35/45/55/70ns
35/45/55/70ns
35/45/55/70ns
35/45/55/70ns
35/45/55/70ns
Power Dissipation
Standby(I
SB1
TYP.) Operating(Icc,TYP.)
5µA (LL)
50/45/40/30mA
5µA (LL)
50/45/40/30mA
5µA (LL)
50/45/40/30mA
5µA (LL)
50/45/40/30mA
5µA (LL)
50/45/40/30mA
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
Vcc
Vss
A0 - A18
DQ0 – DQ7
DECODER
512Kx8
MEMORY ARRAY
CE#
WE#
OE#
V
CC
V
SS
NC
A0-A18
DQ0-DQ7
I/O DATA
CIRCUIT
COLUMN I/O
CE#
WE#
OE#
CONTROL
CIRCUIT
40 Hsuch-Fu Rd., Hsinchu, Taiwan.
TEL: 886-3-5165511
FAX: 886-3-5165522
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
1
®
LY625128
Rev. 2.0
512K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
32
31
30
29
28
Vcc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE#
A17
A15
Vcc
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
LY625128
SOP/P-DIP
6
7
8
9
10
11
12
13
14
15
16
27
26
25
24
23
22
21
20
19
18
17
LY625128
TSOP-I/STSOP
NC
NC
A4
A3
A2
A1
A0
CE#
DQ0
DQ1
Vcc
Vss
DQ2
DQ3
WE#
A18
A17
A16
A15
A14
NC
NC
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
NC
NC
NC
A5
A6
A7
A8
OE#
DQ7
DQ6
Vss
Vcc
DQ5
DQ4
A9
A10
A11
A12
A13
NC
NC
NC
LY625128
9
10
11
12
13
14
15
16
17
18
19
20
21
22
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
B
C
D
E
F
G
H
A0
DQ4
DQ5
Vss
Vcc
DQ6
A1
A2
NC
WE#
NC
A3
A4
A5
A6
A7
A8
DQ0
DQ1
Vcc
Vss
A18
A17
DQ2
A15 DQ3
A13
A14
DQ7 OE# CE# A16
A9
A10
A11
A12
1
TSOP-II
2
3
4
TFBGA
5
6
40 Hsuch-Fu Rd., Hsinchu, Taiwan.
TEL: 886-3-5165511
FAX: 886-3-5165522
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
2
®
LY625128
Rev. 2.0
512K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on V
CC
relative to V
SS
Voltage on any other pin relative to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
T1
V
T2
T
A
T
STG
P
D
I
OUT
T
SOLDER
RATING
-0.5 to 6.5
-0.5 to V
CC
+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
1
50
260
UNIT
V
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
L
L
L
OE#
X
H
L
X
WE#
X
H
H
L
I/O OPERATION
High-Z
High-Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB1
I
CC
,I
CC1
I
CC
,I
CC1
I
CC
,I
CC1
H = V
IH
, L = V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
V
CC
*1
Input High Voltage
V
IH
*1
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
CC
≧
V
IN
≧
V
SS
Output Leakage
V
CC
≧
V
OUT
≧
V
SS
,
I
LO
Current
Output Disabled
Output High Voltage
V
OH
I
OH
= -1mA
Output Low Voltage
V
OL
I
OL
= 2mA
I
CC
Average Operating
Power supply Current
I
CC1
Standby Power
Supply Current
Notes:
MIN.
4.5
2.4
- 0.2
-1
-1
2.4
-
-
-
-
-
-
-
-
TYP.
5.0
-
-
-
-
-
-
50
45
40
30
4
5
5
*3
MAX.
5.5
V
CC
+0.3
0.6
1
1
-
0.4
80
70
60
50
10
25
50
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
µA
µA
I
SB1
- 35
Cycle time = Min.
- 45
CE# = 0.2V, I
I/O
= 0mA
other pins at 0.2V or V
CC
- 0.2V - 55
- 70
Cycle time = 1µs
CE# = 0.2V, I
I/O
= 0mA
other pins at 0.2V or V
CC
- 0.2V
-SL
CE#
≧
V
CC
- 0.2V
Other pins at 0.2V or V
CC
-0.2V -LL
1. V
IH
(max) = V
CC
+ 3.0V for pulse width less than 10ns. V
IL
(min) = V
SS
- 3.0V for pulse width less than 10ns.
2. Over/Undershoot specifications are characterized, not 100% tested.
3. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V
CC
= V
CC
(TYP.) and T
A
= 25℃
40 Hsuch-Fu Rd., Hsinchu, Taiwan.
TEL: 886-3-5165511
FAX: 886-3-5165522
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
3
®
LY625128
Rev. 2.0
512K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
= 25
℃
, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to V
CC
- 0.2V
3ns
1.5V
C
L
= 30pF + 1TTL, I
OH
/I
OL
= -2mA/4mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM. LY625128-35 LY625128-45 LY625128-55 LY625128-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
35
-
45
-
55
-
70
-
ns
Address Access Time
t
AA
-
35
-
45
-
55
-
70
ns
Chip Enable Access Time
t
ACE
-
35
-
45
-
55
-
70
ns
Output Enable Access Time
t
OE
-
25
-
25
-
30
-
35
ns
Chip Enable to Output in Low-Z
t
CLZ
*
10
-
10
-
10
-
10
-
ns
Output Enable to Output in Low-Z t
OLZ
*
5
-
5
-
5
-
5
-
ns
Chip Disable to Output in High-Z t
CHZ
*
-
15
-
20
-
20
-
25
ns
Output Disable to Output in High-Z t
OHZ
*
-
15
-
20
-
20
-
25
ns
Output Hold from Address Change t
OH
10
-
10
-
10
-
10
-
ns
(2) WRITE CYCLE
PARAMETER
SYM. LY625128-35 LY625128-45 LY625128-55 LY625128-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC
35
-
45
-
55
-
70
-
ns
Address Valid to End of Write
t
AW
30
-
40
-
50
-
60
-
ns
Chip Enable to End of Write
t
CW
30
-
40
-
50
-
60
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
25
-
35
-
45
-
55
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
0
-
ns
Data to Write Time Overlap
t
DW
20
-
20
-
25
-
30
-
ns
Data Hold from End of Write Time t
DH
0
-
0
-
0
-
0
-
ns
Output Active from End of Write
t
OW
*
5
-
5
-
5
-
5
-
ns
Write to Output in High-Z
t
WHZ
*
-
15
-
20
-
20
-
25
ns
*These parameters are guaranteed by device characterization, but not production tested.
40 Hsuch-Fu Rd., Hsinchu, Taiwan.
TEL: 886-3-5165511
FAX: 886-3-5165522
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
4
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