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HM5251165BTD-A6

Description
Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
Categorystorage    storage   
File Size1MB,64 Pages
ManufacturerHitachi (Renesas )
Websitehttp://www.renesas.com/eng/
Download Datasheet Parametric View All

HM5251165BTD-A6 Overview

Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

HM5251165BTD-A6 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerHitachi (Renesas )
Parts packaging codeTSOP2
package instructionTSOP2, TSOP54,.46,32
Contacts54
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
JESD-609 codee0
length22.22 mm
memory density536870912 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
Continuous burst length1,2,4,8
Maximum standby current0.004 A
Maximum slew rate0.2 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
Base Number Matches1
HM5251165B-75/A6/B6
HM5251805B-75/A6/B6
HM5251405B-75/A6/B6
512M LVTTL interface SDRAM
133 MHz/100 MHz
8-Mword
×
16-bit
×
4-bank/16-Mword
×
8-bit
×
4-bank
/32-Mword
×
4-bit
×
4-bank
PC/133, PC/100 SDRAM
ADE-203-1095 (Z)
Preliminary
Rev. 0.0
Sep. 1, 1999
Description
The Hitachi HM5251165B is a 512-Mbit SDRAM organized as 8388608-word
×
16-bit
×
4 bank. The
Hitachi HM5251805B is a 512-Mbit SDRAM organized as 16777216-word
×
8-bit
×
4 bank. The Hitachi
HM5251405B is a 512-Mbit SDRAM organized as 33554432-word
×
4-bit
×
4 bank. All inputs and outputs
are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed
RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
Sequential (BL = 1/2/4/8)
Interleave (BL = 1/2/4/8)
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
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