EEWORLDEEWORLDEEWORLD

Part Number

Search

FMXMB1160EFJ-03.200000M-LT

Description
Quartz Crystal,
CategoryPassive components    Crystal/resonator   
File Size260KB,1 Pages
ManufacturerFrequency Management International
Environmental Compliance
Download Datasheet Parametric View All

FMXMB1160EFJ-03.200000M-LT Overview

Quartz Crystal,

FMXMB1160EFJ-03.200000M-LT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid145049000868
package instructionHC-49/US, 2 PIN
Reach Compliance Codecompliant
Ageing5 PPM/YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level50 µW
frequency stability0.002%
frequency tolerance15 ppm
load capacitance60 pF
Installation featuresTHROUGH HOLE MOUNT
Nominal operating frequency3.2 MHz
Maximum operating temperature50 °C
Minimum operating temperature
physical sizeL11.5XB4.65XH4.1 (mm)/L0.453XB0.183XH0.161 (inch)
Series resistance180 Ω
surface mountNO
FMXMB
SERIES
Thru-hole Crystals
Low Profile
Thru-Hole Package
Multiple Package Heights
Low Cost
HC-49/US
SPECIFICATIONS
Issue 6 - 10182012
Parameter
Frequency Range
Operation Mode
Load Capacitance (CL)
Frequency Tolerance
Temperature Tolerance
Operating Temperature
Storage Temperature
Equivalent Series Resistance (ESR)
Shunt Capacitance (C0)
Drive Level
Aging @ 25°C
All specifications subject to change without notice.
Specification
3.2 - 90 MHz
See Operation Mode and ESR Table
18 pF Std., 8 - 60 pF and Series available
±30 ppm @ 25°C Std. (See Cal. Tol. for Options)
±50 ppm Std. (See Temp. Tol. for Options)
0 to +70°C Std. (See Temp. Range for Options)
-55 to +125°C
See Operation Mode and ESR Table
7 pF max.
50 uW typical, 1 mW max.
±5 ppm per year max.
HC-49/US
OPERATION MODE AND ESR TABLE
Frequency (MHz)
3.200 - 5.999
6.000 - 7.999
8.000 - 9.999
10.00 - 14.99
15.000 - 40.000
27.000 - 70.000
MODE
Fundamental
Fundamental
Fundamental
Fundamental
Fundamental
3
rd
Overtone
MAX ESR (Ohms)
180
100
70
60
40
120
DIMENSION “H” TABLE
STANDARD MARKING
FMI XX.XXX
XX.XXX FREQUENCY in MHz
Package
B1
B2
B3
Max. Height
0.161” (4.1mm)
0.126” (3.2mm)
0.118” (3.0mm)
NOTE: Standard Specifications for product indicated in
color
Dimensions:
Inches
(mm)
PART DESCRIPTION SYSTEM
MARKING: See Page 52, Format A
FMXM B1 1 18 H J A - XX.XXXXXXM - CM
Product Family
Crystal
Package
B1,
B2 or B3
Mode
1 - Fundamental
3 - 3rd Overtone
Load Cap. (CL)
18 - Standard (pF)
00 - Series
## - Custom (pF)
Cal.
D
E
F
G
H
I
J
X
Tol. @ 25°C
±10 ppm
±15 ppm
±20 ppm
±25 ppm
±30 ppm
±40 ppm
±50 ppm
Custom
*Temp. Tol.
D ±10 ppm
E ±15 ppm
F ±20 ppm
G ±25 ppm
H ±30 ppm
I ±40 ppm
J ± 50 ppm
X Custom
Frequency (MHz)
Temp. Range
**
A 0 to 70 °C
B -20 to 70 °C
C -40 to 85 °C
D -10 to 50 °C
E -10 to 60 °C
F -30 to 60 °C
J 0 to 50 °C
X Custom
Options
BI - Base Insulator
LT - Lead Trimming
LF - Lead Forming
PD - Parameter Data
TD - Temp. Data
CM - Custom Mark
BLANK - None Req’d.
**Check with us for availability.
-55°C TO +125°C Available, Limited Stability Options,
please consult the factory.
1-800-800-XTAL
[9825]
www.fmi-inc.com
11
Graduation project - 21-digit digital tube perpetual calendar. It doesn't work. There are pictures and the truth. Forgot to ask for help...
The digital tubes show all 8s and nothing happens. However, my chips are not 74ls47 and 74ls138, but 74ls247 and 74HC138... Also, the 240 ohm resistor driving the digital tubes is replaced with 1K. Is...
woainidjh 51mcu
[Challenging SATA RAID Driver] Is there any expert who is familiar with Intel RAIDAHCI Software - How is Intel Matrix Storage Manager implemented?
Question: (1) Where can I find authoritative Raid information? For example, Intel RAID implementation and code, etc. (2) RAID code documentation under Linux, etc. (3) ASUS has launched RAID drivers an...
lvyiyong Embedded System
2010 Guangxi College Student Electronic Design Competition List
[i=s] This post was last edited by paulhyde on 2014-9-15 09:48 [/i] 1. Basic instrument list 20MHz ordinary oscilloscope (dual channel, external trigger input, with X-axis input, optional with Z-axis ...
huangxiao0801 Electronics Design Contest
Does the connection between Cyclone IV FPGA and CAN controller SJA1000 require a level conversion chip?
FPGA's IO is powered by 3.3V, SJA1000 is powered by 5V...
shen19891209 FPGA/CPLD
Xu Jinglei's blog ranks first in the world
Character InformationName: Xu Jinglei Gender: FemaleDate of Birth: 1974.04.16 English name:Zodiac sign: Aries Blood type: OHobbies: music, leisure, sports Height: 168 cmCountry of Citizenship: Birthpl...
gaoyanmei Talking
How to design a delay device using VHDL
The input is some randomly generated signals, and all these input signals are required to be output sequentially after a delay of 100 clock cycles. How should this be designed ? The order of the input...
eeleader-mcu FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1713  910  1373  1650  2320  35  19  28  34  47 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号