TC7WZ74FU/FK
Preliminary
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC7WZ74FU,TC7WZ74FK
D-Type Flip Flop with Preset and Clear
Features
·
·
·
·
·
·
·
High output current: ±24 mA (min) @V
CC
= 3 V
Propagation delay time: t
pd
2.8 ns (typ.) @V
CC
= 3 V, 50 pF
Operating voltage range: V
CC (opr)
= 1.65~5.5 V
High latch-up immunity: ±500 mA or more
High ESD: ±200 V or more (JEITA)
±2000 V or more (MIL)
Power down protection is provided on all inputs.
Electrical characteristics when V
CC
= 3.3 V is the same as
TC74LCX series.
TC7WZ74FK
TC7WZ74FU
Marking
SM8
Type name
US8
Z74
Lot No.
WZ
74
Weight
SSOP8-P-0.65 : 0.02 g (typ.)
SSOP8-P-0.50A : 0.01 g (typ.)
Maximum Ratings
(Ta
=
25°C)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Lead temperature (10s)
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
T
L
Rating
-0.5~6
-0.5~6
-0.5~6
-20
-20
±50
±50
300 (SM8)
200 (US8)
-65~150
260
Unit
Pin Assignment
(top view)
CK 1
V
V
V
mA
mA
mA
mA
mW
°C
°C
GND 4
D 2
PR CLR
Q
8 V
CC
D
CK
7
PR
6
CLR
Q
3
Q
5 Q
1
2001-11-15
TC7WZ74FU/FK
AC Characteristics
(unless otherwise specified, Input: t
r
=
t
f
=
3 ns)
Characteristics
Symbol
Test Condition
V
CC
(V)
1.8
±
0.15
Maximum clock frequency
f
MAX
C
L
=
50 pF, R
L
=
500
W
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
1.8
±
0.15
C
L
=
15 pF, R
L
=
1 MW
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
C
L
=
50 pF, R
L
=
500
W
3.3
±
0.3
5.0
±
0.5
1.8
±
0.15
C
L
=
15 pF, R
L
=
1 MW
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
C
L
=
50 pF, R
L
=
500
W
3.3
±
0.3
5.0
±
0.5
2.5
±
0.2
Minimum setup time
t
s
C
L
=
50 pF, R
L
=
500
W
3.3
±
0.3
5.0
±
0.5
2.5
±
0.2
Minimum hold time
t
h
C
L
=
50 pF, R
L
=
500
W
3.3
±
0.3
5.0
±
0.5
Minimum pulse width
(CK)
t
W
(L)
t
W
(H)
2.5
±
0.2
C
L
=
50 pF, R
L
=
500
W
3.3
±
0.3
5.0
±
0.5
2.5
±
0.2
t
W
(L)
C
L
=
50 pF, R
L
=
500
W
3.3
±
0.3
5.0
±
0.5
2.5
±
0.2
Minimum removal time
t
rem
C
L
=
50 pF, R
L
=
500
W
3.3
±
0.3
5.0
±
0.5
Input capacitance
Output capacitance
Power dissipation
capacitance
C
IN
C
OUT
C
PD
¾
¾
(Note 4)
5.5
0~0.5
0~0.5
3.3
Min
51
130
200
200
2.5
2.0
1.5
1.0
2.0
1.5
2.5
2.0
1.5
1.5
2.0
1.0
3.4
2.1
1.5
2.4
1.4
1.0
3.0
3.0
3.0
3.0
3.0
3.0
3.6
2.2
1.3
¾
¾
¾
¾
Ta
=
25°C
Typ.
¾
¾
¾
¾
10.0
4.9
3.3
2.4
4.3
2.8
10.0
5.0
3.4
2.2
4.3
3.1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
3.0
5.0
30
47
Max
¾
¾
¾
¾
18.0
7.5
4.8
3.5
5.7
4.0
17.0
7.3
4.8
3.5
5.7
3.9
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Ta
= -40~85°C
Min
38
100
150
180
2.1
1.7
1.3
1.0
1.5
1.3
2.1
1.7
1.3
1.0
1.5
1.0
4.1
2.5
1.7
2.9
1.5
1.1
3.6
3.3
3.2
3.6
3.3
3.2
4.4
2.5
1.4
¾
¾
¾
¾
Max
¾
¾
¾
¾
23.0
9.0
5.6
ns
3.9
7.0
4.4
21.0
8.8
5.6
ns
3.9
7.0
4.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
pF
pF
pF
ns
ns
ns
ns
ns
MHz
Unit
Propagation delay time
(CK-Q,
Q
)
t
pLH
t
pHL
Propagation delay time
(
CLR
,
PR
-Q,
Q
)
t
pLH
t
pHL
Minimum pulse width
(
CLR
,
PR
)
Note 4: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
=
C
PD
•V
CC
•f
IN
+
I
CC
4
2001-11-15
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