INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT157
Quad 2-input multiplexer
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Quad 2-input multiplexer
FEATURES
•
Non-inverting data path
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT157 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT157 are quad 2-input multiplexers which
select 4 bits of data from two sources under the control of
a common data select input (S). The four outputs present
the selected data in the true (non-inverted) form. The
enable input (E) is active LOW. When E is HIGH, all of the
outputs (1Y to 4Y) are forced LOW regardless of all other
input conditions.
74HC/HCT157
Moving the data from two groups of registers to four
common output buses is a common use of the “157”. The
state of the common data select input (S) determines the
particular register from which the data comes. It can also
be used as function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
The “157” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations are:
1Y = E.(1l
1
.S + 1l
0
.S)
2Y = E.(2l
1
.S + 2l
0
.S)
3Y = E.(3l
1
.S + 3l
0
.S)
4Y = E.(4l
1
.S + 4l
0
.S)
The “157” is identical to the “158” but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nI
0
, nI
1
to nY
E to nY
S to nY
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
input capacitance
power dissipation capacitance per multiplexer notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
11
11
12
3.5
70
13
12
19
3.5
70
ns
ns
ns
pF
pF
HCT
UNIT
Philips Semiconductors
Product specification
Quad 2-input multiplexer
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
SYMBOL PARAMETER
+25
min.
typ.
max.
74HC/HCT157
TEST CONDITIONS
UNIT
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
74HC
−40
to +85
min.
max.
−40
to +125
min.
max.
t
PHL
/ t
PLH
propagation delay
nI
0
to nY;
nI
1
to nY
propagation delay
E to nY
propagation delay
S to nY
output transition
time
36
13
10
39
14
11
41
15
12
19
7
6
125
25
21
115
23
20
125
25
21
75
15
13
155
31
26
145
29
25
155
31
26
95
19
16
190
38
32
175
35
30
190
38
32
110
22
19
ns
t
PHL
/ t
PLH
ns
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6 and Fig.7
December 1990
5
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