400MHz Low Voltage PECL Clock
Synthesizer w/Spread Spectrum
Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)
The MPC92469 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance tele-
com, networking and computing applications. With output frequencies from
25 MHz to 400 MHz and the support of differential PECL output signals the
device meets the needs of the most demanding clock applications.
Features
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25 MHz to 400 MHz synthesized clock output signal
Differential PECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Spread Spectrum output for EMI reduction
3.3 V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
32-lead LQFP packaging
32-lead Pb-free package available
SiGe Technology
Ambient temperature range 0C to +70C
Pin compatible to the MC12429, MPC9229, MPC92429, and ICS84329
MPC92469
DATASHEET
400 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
w/SPREAD SPECTRUM
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of
its frequency reference. The frequency of the internal crystal oscillator is divided
by 16 and then multiplied by the PLL. The VCO within the PLL operates over a
range of 400 to 800 MHz. Its output is scaled by a divider that is configured by
either the serial or parallel interfaces. The crystal oscillator frequency f
XTAL
, the
PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 2M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (400 to 800 MHz). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50
to V
CC
– 2.0 V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a eighteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See
PROGRAM-
MING INTERFACE
for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]
bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC92469 REVISION 4 FEBRUARY 6, 2013
1
©2013 Integrated Device Technology, Inc.
MPC92469 Data Sheet
400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PACKAGE DIMENSIONS
V
CC
OE
XTAL_IN
XTAL_OUT
XTAL
12 – 20 MHz
16
Ref
VCO
2
PLL
400 – 800 MHz
FB
1
2
4
8
00
01
10
11
OE
FOUT
FOUT
SYNC
9-BIT M-DIVIDER
9
V
CC
P_LOAD
S_LOAD
LE
P/S
V
CC
BITS 9-17
M[0:8]
N[1:0]
S_DATA
S_CLOCK
18-BIT SHIFT REGISTER
1
0
BITS 7-8
1
0
M-LATCH
2
N-LATCH
TEST
3
T-LATCH
SSM-LATCH
TEST
BITS 4-6
BITS 0-3
Figure 1. MPC92469 Logic Diagram
M[8]
M[7]
M[6]
M[5]
18
24
GND
TEST
V
CC
V
CC
GND
FOUT
FOUT
V
CC
25
26
27
28
29
30
31
32
1
23
22
21
20
19
M[4]
17
16
15
14
NC
M[3]
M[2]
M[1]
M[0]
P_LOAD
OE
XTAL_OUT
13
12
11
10
9
8
XTAL_IN
N[1]
2
N[0]
3
NC
MPC92469
4
5
6
7
S_CLOCK
S_DATA
NC
S_LOAD
V
CC_PLL
Figure 2. MPC92469 32-Lead Package Pinout
MPC92469 REVISION 4 FEBRUARY 6, 2013
2
©2013 Integrated Device Technology, Inc.
V
CC_PLL
NC
MPC92469 Data Sheet
400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
(Top View)
Table 1. Pin Configurations
Pin
XTAL_IN, XTAL_OUT
FOUT, FOUT
TEST
S_LOAD
Output
Output
Input
0
I/O
Default
Type
Analog
LVPECL
LVCMOS
LVCMOS
Crystal oscillator interface.
Differential clock output.
Test and device diagnosis output.
Serial configuration control input.
This inputs controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive.
Serial configuration data input.
Serial configuration clock input.
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD.
Output enable (active high).
The output enable is synchronous to the output clock to eliminate the possibility
of runt pulses on the F
OUT
output. OE = L low stops F
OUT
in the logic low state
(F
OUT
= L, FOUT = H).
Negative power supply (GND).
Positive power supply for I/O and core. All V
CC
pins must be connected to the
positive power supply for correct operation.
PLL positive power supply (analog power supply).
Function
P_LOAD
Input
1
LVCMOS
S_DATA
S_CLOCK
M[8:0]
N[1:0]
OE
Input
Input
Input
Input
Input
0
0
1
1
1
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
GND
V
CC
V
CC_PLL
Supply
Supply
Supply
Supply
Supply
Supply
Ground
V
CC
V
CC
Table 2. Output Frequency Range and PLL Post-Divider N
N
N1
0
0
1
1
N0
0
1
0
1
Output Division
1
2
4
8
Output Frequency Range
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
MPC92469 REVISION 4 FEBRUARY 6, 2013
3
©2013 Integrated Device Technology, Inc.
MPC92469 Data Sheet
400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
Table 3. General Specifications
Symbol
V
TT
MM
HBM
LU
C
IN
JA
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Input Capacitance
LQFP 32 Thermal Resistance Junction to Ambient
Single layer test board
200
2000
200
4.0
67.8
55.9
50.1
47.9
42.1
39.4
23.0
26.3
Min
Typ
V
CC
– 2
Max
Unit
V
V
V
mA
pF
C/W
C/W
C/W
C/W
C/W
C/W
C/W
Inputs
0 lfpm
200 lfpm
500 lfpm
0 lfpm
200 lfpm
500 lfpm
MIL-SPEC 883E
Method 1012.1
Condition
Multi-layer test board
JC
LQFP 32 Thermal Resistance Junction to Case
Table 4. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
20
50
125
Unit
V
V
V
mA
mA
C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
V
IH
V
IL
I
IN
V
OH
V
OL
V
OH
V
OL
I
CC_PLL
I
CC
Input High Voltage
Input Low Voltage
Input Current
(1)
Output High Voltage
(3)
Output Low Voltage
(3)
Output High Voltage
(3)
Output Low Voltage
(3)
2.0
V
CC
+ 0.3
0.8
200
V
V
A
LVCMOS
LVCMOS
V
IN
= V
CC
or GND
LVPECL
LVPECL
Differential Clock Output F
OUT(2)
V
CC
–1.11
V
CC
–1.95
2.0
0.55
V
CC
–0.74
V
CC
–1.60
V
V
Test and Diagnosis Output TEST
V
V
I
OH
= –0.8 mA
I
OH
= 0.8 mA
V
CC_PLL
Pins
All V
CC
Pins
Supply Current
Maximum PLL Supply Current
Maximum Supply Current
8
95
mA
mA
1. Inputs have pull-down resistors affecting the input current.
2. Outputs terminated 50
to V
TT
= V
CC
– 2 V.
3. The MPC92469 TEST output levels are compatible to the MC12429 output levels.
MPC92469 REVISION 4 FEBRUARY 6, 2013
4
©2013 Integrated Device Technology, Inc.
MPC92469 Data Sheet
400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
Table 6. AC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
(1)
Symbol
f
XTAL
f
VCO
f
MAX
Characteristics
Crystal Interface Frequency Range
VCO Frequency Range
(2)
Output Frequency
N = 00 (1)
N = 01 (2)
N = 10 (4)
N = 11 (8)
Min
12
400
200
100
50
25
48
0.05
50
Typ
Max
20
800
400
200
100
50
52
0.3
10
50
20
20
20
20
20
50
50
10
32
SS[3:0] = 0001
SS[3:0] = 1001
±0.30
-0.3
±0.5
-0.5
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
MHz
ns
ns
ns
ns
ns
ns
ps
ps
ms
kHz
%
%
f
XTAL
= 16 MHz
f
out
= 300 MHz
f
XTAL
= 16 MHz
N
8
N
8
20% to 80%
Condition
DC
t
r
, t
f
f
S_CLOCK
t
P,MIN
t
S
Output Duty Cycle
Output Rise/Fall Time
Serial Interface Programming Clock Frequency
(3)
Minimum Pulse Width
Setup Time
(S_LOAD, P_LOAD)
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
S_DATA to S_CLOCK
M, N to P_LOAD
t
S
t
JIT(CC)
t
JIT(PER)
t
LOCK
SSM
fmod
SSM
dev
Hold Time
Cycle-to-Cycle Jitter
Period Jitter
Maximum PLL Lock Time
Spread Spectrum Modulation Frequency
Spread Spectrum Modulation Deviation
1. AC characteristics apply for parallel output termination of 50
to V
TT
.
2. The input frequency f
XTAL
and the PLL feedback divider M must match the VCO frequency range: f
VCO
= f
XTAL
x M
8.
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See
APPLICATIONS INFORMATION
for more details.
MPC92469 REVISION 4 FEBRUARY 6, 2013
5
©2013 Integrated Device Technology, Inc.
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