MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC88LV915T/D
Rev 3, 08/2001
Low Voltage Low Skew CMOS
PLL Clock Driver, 3-State
The MC88LV915T Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for high performance PC’s
and workstations.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
components on a board. The PLL also allows the MC88LV915T to multiply
a low frequency input clock and distribute it locally at a higher (2X) system
frequency. Multiple 88LV915’s can lock onto a single reference clock, which
is ideal for applications when a central system clock must be distributed
synchronously to multiple boards (see Figure 4 on Page 9).
MC88LV915T
LOW SKEW CMOS
PLL CLOCK DRIVER
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°
phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”
frequency.
The VCO is designed to run optimally between 20 MHz and the 2X_Q F
max
specification. The wiring diagrams in Figure 2 detail
the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the
“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1
and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on
page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding
FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz).
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88LV915T in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing
(see detailed description on page 11).
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the
OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go
low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88LV915 sees
a SYNC signal and full 5V V
CC
.
•
Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
•
The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t
PD
specification, which defines the part–to–part skew)
•
Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available
•
Input frequency range from 5MHz – 2X_Q FMAX spec.
•
Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available
•
All outputs have
±36
mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are
TTL–level compatible.
±88mA
I
OL
/I
OH
specifications guarantee 50Ω transmission line switching on the incident edge
•
Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.
All outputs can go into high impedance (3–state) for board test purposes
•
Lock Indicator (LOCK) accuracy indicates a phase–locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
Features
©
Motorola, Inc. 2001
t
Pinout: 28–Lead PLCC
(Top View)
OE/RST V
CC
4
FEEDBACK
REF_SEL
SYNC[0]
V
CC
(AN)
RC1
GND(AN)
SYNC[1]
5
6
7
8
9
10
11
12
13
14
Q0
15
V
CC
16
Q1
17
GND
18
PLL_EN
3
Q5
2
GND
1
Q4
28
V
CC
27
2X_Q
26
25
24
23
22
21
20
19
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
FREQ_SEL GND
FN SUFFIX
PLASTIC PLCC
CASE 776–02
PIN SUMMARY
Pin Name
Num
I/O
Function
SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0-4)
Q5
2x_Q
Q/2
LOCK
OE/RST
PLL_EN
V
CC
,GND
1
1
1
1
1
1
5
1
1
1
1
1
1
11
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Reference clock input
Reference clock input
Chooses reference between sync[0] & Sync[1]
Doubles VCO Internal Frequency (low)
Feedback input to phase detector
Input for external RC network
Clock output (locked to sync)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output(Q) frequency
÷
2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Output Enable/Asynchronous reset (active low)
Disables phase-lock for low freq. testing
Power and ground pins (note pins 8, 10 are
analog" supply pins for internal PLL only)
2
MOTOROLA
MC88LV915T BLOCK DIAGRAM
LOCK
FEEDBACK
SYNC (0)
0
SYNC (1)
M
U
1 X
PHASE/FREQ.
DETECTOR
CHARGE PUMP/LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
REF_SEL
EXTERNAL REC NETWORK
(RC1 Pin)
PLL_EN
0
MUX
1
2x_Q
D
(÷1)
1
DIVIDE
BY TWO
(÷2)
M
U
0 X
CP
R
Q
Q
Q0
D
CP
R
Q
Q1
FREQ_SEL
OE/RST
D
CP
R
Q
Q2
D
CP
R
Q
Q3
D
CP
R
Q
Q4
D
CP
R
Q
Q5
D
CP
R
Q
Q/2
MOTOROLA
3
MAXIMUM RATINGS*
Symbol
V
CC
, AV
CC
V
in
V
out
I
in
I
out
I
CC
T
stg
Parameter
DC Supply Voltage Referenced to GND
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, Per Pin
DC Output Sink/Source Current, Per Pin
DC V
CC
or GND Current Per Output Pin
Storage Temperature
Limits
–0.5 to 7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
±20
±50
±50
–65 to +150
Unit
V
V
V
mA
mA
mA
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
V
out
T
A
ESD
Supply Voltage
DC Input Voltage
DC Output Voltage
Ambient Operating Temperature
Static Discharge Voltage
Parameter
Limits
3.3
±0.3
0 to V
CC
0 to V
CC
0 to 70
> 1000
Unit
V
V
V
°C
V
DC CHARACTERISTICS
(T
A
= 0°C to 70°C; V
CC
= 3.3V
±
0.3V)
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
I
CCT
I
OLD
I
OHD
I
CC
Maximum Quiescent Supply Current
Parameter
Minimum High Level Input Voltage
Minimum Low Level Input Voltage
Minimum High Level Output Voltage
Minimum Low Level Output Voltage
Maximum Input Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
3
Output Current
V
CC
3.0
3.3
3.0
3.3
3.0
3.3
3.0
3.3
3.6
3.6
3.6
3.6
3.6
Guaranteed Limits
2.0
2.0
0.8
0.8
2.4
2.7
0.44
0.44
±1.0
2.0
+50
–50
TBD
Unit
V
V
V
V
µA
mA
mA
mA
µA
Condition
V
OUT
= 0.1V or
V
CC
– 0.1V
V
OUT
= 0.1V or
V
CC
– 0.1V
V
IN
= V
IH
or V
IL
I
OH
= –24mA
V
IN
= V
IH
or V
IL
I
OH
= 24mA
V
I
= V
CC
, GND
V
I
= V
CC
– 2.1V
V
OLD
= 1.25V
V
OHD
=2.35V
V
I
= V
CC
, GND
1. I
OL
is +12mA for the RST_OUT output.
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration 2.0ms, one output loaded at a time.
SYNC INPUT TIMING REQUIREMENTS
Symbol
t
RISE/FALL
SYNC Input
t
CYCLE
,
SYNC Input
Duty Cycle
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
Input Clock Period
SYNC Input
Duty Cycle, SYNC Input
Parameter
Minimum
—
Maximum
5.0
Unit
ns
1
f2X_Q 4
50%
±
25%
100
ns
4
MOTOROLA
FREQUENCY SPECIFICATIONS
(T
A
= 0°C to 70°C; V
CC
= 3.3V
±
0.3V)
Symbol
Fmax (2X_Q)
Fmax (‘Q’)
Parameter
Maximum Operating Frequency, 2X_Q Output
Maximum Operating Frequency,
Q0–Q3 Outputs
Guaranteed Minimum
100
50
Unit
MHz
MHz
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition.
AC CHARACTERISTICS
(T
A
=0° C to +70° C, V
CC
= 3.3V
±0.3V,
Load = 50Ω Terminated to V
CC
/2)
Symbol
t
RISE/FALL
Outputs
t
PULSE WIDTH
(Q0–Q4, Q5, Q/2)
t
PULSE WIDTH
(2X_Q Output)
Parameter
Rise/Fall Time, All Outputs
(Between 0.8 to 2.0V)
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
Q5, Q/2 @ V
CC
/2
Output Pulse Width:
2X_Q @ 1.5V
40MHz
66MHz
80MHz
100MHz
40MHz
66MHz
80MHz
100MHz
Min
0.5
0.5t
CYCLE
– 0.5
1
0.5t
CYCLE
– 1.5
0.5t
CYCLE
– 1.0
0.5t
CYCLE
– 1.0
0.5t
CYCLE
– 1.0
t
CYCLE
– 600ps
t
CYCLE
– 300ps
t
CYCLE
– 300ps
t
CYCLE
– 400ps
Max
2.0
0.5t
CYCLE
+ 0.5
1
0.5t
CYCLE
+ 0.5
0.5t
CYCLE
+ 0.5
0.5t
CYCLE
+ 0.5
0.5t
CYCLE
+ 0.5
t
CYCLE
+ 600ps
t
CYCLE
+ 300ps
t
CYCLE
+ 300ps
t
CYCLE
+ 400ps
ns
Unit
ns
ns
ns
Condition
Into a 50Ω Load
Terminated to V
CC
/2
Into a 50Ω Load
Terminated to V
CC
/2
Into a 50Ω Load
Terminated to V
CC
/2
t
CYCLE
(2x_Q Output)
Cycle–to–Cycle Variation
2x_Q @ V
CC
/2
t
PD
2
SYNC F db k
Feedback
(With 1MΩ from RC1 to An V
CC
)
SYNC Input to Feedback Delay 66MHz
(Measured at SYNC0 or 1 and
80MHz
FEEDBACK Input Pins)
100MHz
Output–to–Output Skew Between Outputs
Q0–Q4, Q/2 (Rising Edges Only)
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
–1.65
–1.45
–1.25
—
–1.05
–0.85
–0.65
500
t
SKEWr
3
(Rising) See Note
4
t
SKEWf
3
(Falling)
t
SKEWall
3
ps
All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
Also Time to LOCK
Indicator High
Measured With the
PLL_EN Pin Low
Measured With the
PLL_EN Pin Low
—
750
ps
—
750
ps
t
LOCK
4
1.0
10
ms
t
PZL
5
t
PHZ
,t
PLZ
5
1.
2.
3.
4.
3.0
3.0
14
14
ns
ns
T
CYCLE
in this spec is 1/Frequency at which the particular output is running.
The T
PD
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
Under equally loaded conditions and at a fixed temperature and voltage.
With V
CC
fully powered–on, and an output properly connected to the FEEDBACK pin. t
LOCK
maximum is with C1 = 0.1µF, t
LOCK
minimum is with
C1 = 0.01µF.
5. The t
PZL
, t
PHZ
, t
PLZ
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
MOTOROLA
5
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