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SI5316-B-GM

Description
IC prec jitter attenuator 36qfn
CategoryWireless rf/communication    Telecom circuit   
File Size1MB,40 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
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SI5316-B-GM Overview

IC prec jitter attenuator 36qfn

SI5316-B-GM Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Parts packaging codeQFN
package instructionHVQCCN,
Contacts36
Reach Compliance Codeunknown
appSONET;SDH
JESD-30 codeS-XQCC-N36
length6 mm
Number of functions1
Number of terminals36
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height0.9 mm
Nominal supply voltage1.8 V
surface mountYES
Telecom integrated circuit typesATM/SONET/SDH SUPPORT CIRCUIT
Temperature levelINDUSTRIAL
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width6 mm
Si5323
P
I N
- P
ROGRAMMABLE
P
R E C I S I O N
C
LOCK
M
ULTIPLIER
/J
I T T E R
A
TTENUA TOR
Features
Pin-selectable output frequencies
ranging from 8 kHz–708 MHz
Ultra-low jitter clock outputs as low
as 250 fs rms (12 kHz–20 MHz)
270 fs rms (50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz–8.4 kHz)
Meets ITU-T G.8251 and Telcordia
OC-192 GR-253-CORE jitter
specifications
Hitless input clock switching with
phase build-out and digital hold
Dual clock outputs with selectable
signal format (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 FEC ratios
(255/238, 255/237, 255/236)
LOL, LOS alarm outputs
Pin-controlled output phase adjust
Single supply 1.8 ±5%, 2.5 or 3.3 V
±10% operation with high PSRR
On-chip voltage regulator
Small size: 6 x 6 mm 36-lead QFN
Ordering Information:
See page 33.
Applications
SONET/SDH OC-48/STM-16 and
OC-192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
Pin Assignments
ITU G.709 line cards
Optical modules
Test and measurement
Synchronous Ethernet
RST 1
FRQTBL
2
CKOUT1–
CKOUT2+
CKOUT2–
36 35 34 33 32 31 30 29 28
27 FRQSEL3
26 FRQSEL2
25 FRQSEL1
Description
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed
communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to
1050 MHz. The input clock frequency and clock multiplication ratio are selectable
from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is
based on Silicon Laboratories' 3rd-generation DSPLL
®
technology, which
provides any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V
supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in
high performance timing applications.
C1B 3
C2B 4
VDD 5
XA 6
XB
7
NC
GND
CKOUT1+
24 FRQSEL0
23 BWSEL1
22 BWSEL0
21 CS_CA
20 INC
19 DEC
LOL
SFOUT0
GND
Pad
GND 8
AUTOSEL 9
10 11 12 13 14 15 16 17 18
CKIN2+
DBL2_BY
CKIN1+
CKIN1–
VDD
RATE0
CKIN2–
RATE1
Functional Block Diagram
Xtal or Refclock
CKIN1
CKOUT1
DSPLL
CKIN2
®
Signal Format
CKOUT2
Disable/BYPASS
Loss of Signal
Loss of Lock
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency Select
Bandwidth Select
Rate Select
Manual/Auto Switch
/
Clock Select
Skew Control
Rev. 1.0 1/11
Copyright © 2011 by Silicon Laboratories
SFOUT1
VDD
Si5323

SI5316-B-GM Related Products

SI5316-B-GM SI5323-B-GM SI5323-C-GMR
Description IC prec jitter attenuator 36qfn IC multiplier/attenuator 36qfn IC MULTIPLIER/ATTENUATOR 36-QFN
Is it Rohs certified? conform to conform to conform to
Maker Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc
Parts packaging code QFN QFN QFN
package instruction HVQCCN, HVQCCN, QFN-36
Contacts 36 36 36
Reach Compliance Code unknown unknown compliant
app SONET;SDH SONET;SDH SONET;SDH
JESD-30 code S-XQCC-N36 S-XQCC-N36 S-XQCC-N36
length 6 mm 6 mm 6 mm
Number of functions 1 1 1
Number of terminals 36 36 36
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED
encapsulated code HVQCCN HVQCCN HVQCCN
Package shape SQUARE SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 NOT SPECIFIED
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 0.9 mm 0.9 mm 0.9 mm
Nominal supply voltage 1.8 V 1.8 V 1.8 V
surface mount YES YES YES
Telecom integrated circuit types ATM/SONET/SDH SUPPORT CIRCUIT ATM/SONET/SDH SUPPORT CIRCUIT ATM/SONET/SDH SUPPORT CIRCUIT
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form NO LEAD NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm 0.5 mm
Terminal location QUAD QUAD QUAD
Maximum time at peak reflow temperature 40 40 NOT SPECIFIED
width 6 mm 6 mm 6 mm
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