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NB2308AI2DT

Description
IC buffer clk 8out 3.3V 16-tssop
Categorylogic    logic   
File Size168KB,13 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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NB2308AI2DT Overview

IC buffer clk 8out 3.3V 16-tssop

NB2308AI2DT Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP16,.25
Contacts16
Reach Compliance Codeunknown
series2308
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
JESD-609 codee4
length5 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
MaximumI(ol)0.008 A
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.4 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
minfmax133.3 MHz
NB2308A
3.3 V Zero Delay
Clock Buffer
The NB2308A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks. It is available in a 16 pin package. The
part has an on−chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The input−to−output
propagation delay is guaranteed to be less than 250 ps, and the
output−to−output skew is guaranteed to be less than 200 ps.
The NB2308A has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three−stated. The select input also allows the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2308A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
The NB2308A is available in five different configurations (Refer to
NB2308A Configurations Table). The NB2308Ax1* is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2308Ax1H is the high−drive version of
the
−1
and the rise and fall times on this device are much faster.
The NB2308Ax2 allows the user to obtain 2X and 1X frequencies
on each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. The NB2308Ax3
allows the user to obtain 4X and 2X frequencies on the outputs.
The NB2308Ax4 enables the user to obtain 2X clocks on all outputs.
Thus, the part is extremely versatile, and can be used in a variety of
applications.
The NB2308Ax5H is a high−drive version with REF/2 on both
banks.
Features
http://onsemi.com
MARKING
DIAGRAMS*
16
1
SOIC−16
D SUFFIX
CASE 751B
1
XXXXXXXXXG
AWLYWW
16
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
XXXX
XXXX
ALYWG
G
XXXX = Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Zero Input
Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
Multiple Configurations
Refer to NB2308A Configurations Table
Input Frequency Range: 15 MHz to 133 MHz
Multiple Low−Skew Outputs
Output−Output Skew Less than 200 ps
Device−Device Skew Less than 700 ps
Two banks of four outputs, three−stateable by two select inputs
Less than 200 ps Cycle−to−Cycle Jitter
Available in 16−pin SOIC and TSSOP Packages
3.3V operation
Advanced 0.35
m
CMOS Technology
Pb−Free Packages are Available**
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*x = C for Commercial; I for Industrial.
**For additional information on our Pb−Free strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
November, 2005
Rev. 2
1
Publication Order Number:
NB2308A/D

NB2308AI2DT Related Products

NB2308AI2DT NB2308AI1HD NB2308AI2D NB2308AI1HDT NB2308AI4D NB2308AC1HD NB2308AC1HDT NB2308AC4D
Description IC buffer clk 8out 3.3V 16-tssop IC buffer clk 8out 3.3V 16-soic IC buffer clk 8out 3.3V 16-soic IC buffer clk 8out 3.3V 16-tssop IC buffer clk 8out 3.3V 16-soic IC buffer clk 8out 3.3V 16-soic IC buffer clk 8out 3.3V 16-tssop IC buffer clk 8out 3.3V 16-soic
Is it lead-free? Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead
Is it Rohs certified? conform to incompatible incompatible conform to incompatible incompatible conform to incompatible
Parts packaging code TSSOP SOIC SOIC TSSOP SOIC SOIC TSSOP SOIC
package instruction TSSOP, TSSOP16,.25 SOP, SOP16,.25 SOP, SOP16,.25 TSSOP, TSSOP16,.25 SOP, SOP16,.25 SOP, SOP16,.25 TSSOP-16 SOP, SOP16,.25
Contacts 16 16 16 16 16 16 16 16
Reach Compliance Code unknown not_compliant not_compliant unknown not_compliant not_compliant unknown not_compliant
series 2308 2308 2308 2308 2308 2308 2308 2308
Input adjustment STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e4 e0 e0 e4 e0 e0 e4 e0
length 5 mm 9.9 mm 9.9 mm 5 mm 9.9 mm 9.9 mm 5 mm 9.9 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
MaximumI(ol) 0.008 A 0.012 A 0.008 A 0.012 A 0.008 A 0.012 A 0.012 A 0.008 A
Number of functions 1 1 1 1 1 1 1 1
Number of terminals 16 16 16 16 16 16 16 16
Actual output times 8 8 8 8 8 8 8 8
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 70 °C 70 °C 70 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C - - -
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SOP SOP TSSOP SOP SOP TSSOP SOP
Encapsulate equivalent code TSSOP16,.25 SOP16,.25 SOP16,.25 TSSOP16,.25 SOP16,.25 SOP16,.25 TSSOP16,.25 SOP16,.25
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED 240 240 NOT SPECIFIED 240 240 NOT SPECIFIED 240
power supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.4 ns 0.2 ns 0.4 ns 0.2 ns 0.2 ns 0.2 ns 0.2 ns 0.2 ns
Maximum seat height 1.2 mm 1.75 mm 1.75 mm 1.2 mm 1.75 mm 1.75 mm 1.2 mm 1.75 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Tin/Lead (Sn80Pb20) Tin/Lead (Sn80Pb20) Nickel/Palladium/Gold (Ni/Pd/Au) Tin/Lead (Sn80Pb20) Tin/Lead (Sn80Pb20) Nickel/Palladium/Gold (Ni/Pd/Au) Tin/Lead (Sn80Pb20)
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 1.27 mm 1.27 mm 0.65 mm 1.27 mm 1.27 mm 0.65 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED 30 30 NOT SPECIFIED 30 30 NOT SPECIFIED 30
width 4.4 mm 3.9 mm 3.9 mm 4.4 mm 3.9 mm 3.9 mm 4.4 mm 3.9 mm
minfmax 133.3 MHz 133.3 MHz 133.3 MHz 133.3 MHz 133.3 MHz 133.3 MHz 133.3 MHz 133.3 MHz
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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