OW Type
5.0 x 3.2 mm SMD LVPECL/LVDS/
HCSL Crystal Oscillator
FEATURE
- Typical 5.0 x 3.2 x 1.25 mm hermetically sealed ceramic package.
- Very low jitter performance: typical 0.3 pS RMS from 12 k - 20 MHz.
- Fundamental/3rd overtone crystal design.
- Output frequency up to 320 MHz.
。
- Operating temperature up to 125 C
- Tri-state enable/disable
TYPICAL APPLICATION
- 10Gbit Ethernet, Fiber Channel, Storage Area Network, SONET
- Enterprise Servers, Reference clocks for ADC and DAC
- Telecom
DIMENSION (mm)
[ TOP VIEW ]
5.00 ± 0.15
#6
#5 #4
Actual Size
RoHS Compliant
SOLDER PAD L AYOUT (mm)
[ BOTTOM VIEW ]
2.54 ± 0.15
#4
#5
#6
2.54
3.20 ± 0.15
2.10 ± 0.15
0.90 ± 0.15
[ SIDE VIEW ]
1.25 ± 0.10
0.55
Pin#
1
2
3
4
5
6
Function
Tri-State
NC
GND
Output
Comp.Output
V
DD
1.20
#1
#2 #3
#3
#2 #1
0.64 ± 0.15
0.90
To ensure optimal oscillator performance, place a by-pass capacitor of 0.1
μF
as close to the part as possible between Vdd and GND pads.
ELECTRICAL SPECIFICATION
Parameter
Supply Voltage Variation (V
DD
)
Frequency Range
Standard Frequency
Supply Current
10 MHz Fo
160 MHz Fo
250 MHz Fo
Output Level
Output High
Output Low
LVPECL
3.3 V
2.5 V
Min.
Max.
Min.
Max.
10
_
_
_
2.275
_
_
_
_
320
10
25, 106.25,
_
_
_
1.475
_
_
_
LVDS
3.3 V
2.5 V
Min.
Max.
Min.
Max.
320
50
50
65
_
unit
V
MHz
mA
V
nSec
mSec
V
V
DD -5%
V
DD+5%
V
DD -5%
V
DD+5%
V
DD -5%
V
DD+5%
V
DD -5%
V
DD+5%
160 MHz
250 MHz
320 MHz
75
100
100
_
1.68
1.0
Transition Time: Rise/Fall Time+
Start Time
Tri-State(Input to Pin 2 or Pin 1)
Enable (High voltage or floating)
Disable (Low voltage or GND)
RMS Phase Jitter (Integrated 12 KHz ~ 20 MHz)
Fo < 80 MHz
80 MHz Fo <125 MHz
125 MHz Fo <170 MHz
170 MHz Fo <200 MHz
200 MHz Fo
Phase Noise@ 156.25 MHz
100 Hz
1 kHz
10 kHz
Aging (@ 25°C 1st year)
Storage Temp. Range
320
10
320
10
125, 156.25, 161.1328, 212.5
_
_
75
50
_
_
100
50
_
_
100
65
_
_
_
1.6
_
0.88
0.9
0.9
1.0
2.10
0.1 µF
1.6
1.0
10
_
10
_
_
_
1.0
10
_
_
_
10
_
2.31
0.99
1
1.75
_
0.75
1
2.31
_
0.99
1.75
_
0.75
1
_
_
_
_
_
-95
-125
-140
0.5
0.3
0.5
0.3
_
_
_
_
_
-90
-125
-140
0.5
0.3
0.5
0.3
_
_
_
_
_
-90
-120
-140
0.5
0.3
0.5
0.3
1
_
_
_
_
_
-90
-120
-140
0.5
0.3
0.5
0.3
pSec
dBc/Hz
±3
125
ppm
°C
_
-55
±3
125
_
-55
±3
125
_
-55
±3
125
_
-55
Note: not all combination of options are available. Other specifications may be available upon request.
Specifications subject to change without notice.
www.taitien.com
sales@taitien.com.tw
Rev(11) 09/2021
61
Parameter
Supply Voltage Variation (V
DD
)
Frequency Range
Standard Frequency
Supply Current
25 MHz Fo 175 MHz
Output Level
Output High
Output Low
Transition Time: Rise/Fall Time+
Start Time
Tri-State(Input to Pin 2 or Pin 1)
Enable
Disable
RMS Phase Jitter (Integrated 12 kHz ~ 20 MHz)
25MHz
≦
Fo
≦
175MHz
Aging
Storage Temp. Range
V
DD-5%
25
_
0.6
_
_
_
0.7
V
DD
_
_
_
-55
Min.
3.3 V
HCSL
Max.
175
50
_
0.15
V
DD+5%
100
V
DD-5%
25
_
0.58
_
_
_
0.7
V
DD
_
_
_
-55
Min.
2.5 V
V
DD+5%
175
50
_
0.15
Max.
unit
V
MHz
mA
V
nSec
mSec
V
pSec
ppm
°C
0.5
10
_
0.5
10
_
0.3
V
DD
0.5
125
±3
0.3
V
DD
0.5
125
±3
FREQ. STABILITY vs. TEMP. RANGE
Temp. (°C)
ppm
±25
±50
*
-40 ~ +85
-10 ~ +60
-20 ~ +70
-40 ~ +125
*
Inclusive of calibration @ 25 °C, operating temperature range, input
voltage variation, load variation, aging (1
st
year), shock, and vibration
○
: Available
△:Conditional
X: Not available
Note: not all combination of options are available. Other specifications may be available upon request.
62
Specifications subject to change without notice.
www.taitien.com
sales@taitien.com.tw
Rev(11) 09/2021
Embedded System
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