531FC830M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531FC830M000DGR

531FC830M000DGR: DescriptionLVDS Output Clock Oscillator, 830MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531FC830M000DGR Overview

LVDS Output Clock Oscillator, 830MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531FC830M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	830 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

A microcontroller infrared asynchronous communication port circuit diagram

The process and phase relationship of the driving signal from t1 to t2 (120° to 240°)

Novel temperature controller circuit

±8V, -16V regulated power supply circuit

Infrared remote control dimmer light circuit diagram

M67 type infrared sensor signal flow circuit diagram

【Let's play ble+zigbee+6lowpan together! 】—Our TI-CC26xx runs TI-RTOS to light up the LED and LCD: [i=s] 本帖最后由 damiaa 于 2015-12-1 18:39 编辑 [/i]【一起来玩ble+zigbee+6lowpan！】—我们的TI-CC26xx跑TI-RTOS [font=Microsoft Yahei, Hei, Tahoma, SimHei, sans-serif][size=3][b]点亮了LED[/b][/size][/font]Example Summary ---...; damiaa RF/Wirelessly

Vivado Learning 2- Custom IP Core: Continue from the previous post Vivado Learning 1- Error in calling and instantiating IP - FPGA/CPLD - Electronic Engineering World - Forum [url=https://bbs.eeworld.com.cn/thread-508046-1-1.html]https...; suoma FPGA/CPLD

Application of EPS emergency power supply in electrical design: Application of EPS emergency power supply in electrical design According to national standards, power loads are divided into level one, level two, and level three loads according to their importance a...; 破茧佼龙 Power technology

Questions about CAN bus: If all nodes on the CAN are isolated, where does the power supply on the bus come from? For example, if I want the logic level on the CAN to be 24V, where does this 24V go?...; huo_hu MCU

Doubts about the response of MC55 sending data in GPRS module: Hello everyone, I encountered a problem and was confused when testing MC55. The problem is this: I need the lower computer to transmit data packets to the upper computer through the GPRS wireless netw...; SHOWA Embedded System

Are you interested in Lierda's TI development board Cotex-A8 AM1808 development board?: Are you interested in Lierda's TI development board Cotex-A8 AM1808 development board?...; whctx DSP and ARM Processors

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components