FS6131
Programmable Line Lock Clock Generator IC
1.0 Key Features
•
•
•
•
Complete programmable control via I
2
C™-bus
Selectable CMOS or PECL compatible outputs
External feedback loop capability allows genlocking
Tunable VCXO loop for jitter attenuation
2.0 General Description
The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of
2
electronic systems. Via the I C-bus interface, the FS6131-01 can be adapted to many clock generation requirements.
The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feed-back dividers, their
granularity, and the flexibility of the post divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock
generator available.
3.0 Applications
•
•
•
•
Frequency synthesis
Line-locked and genlock applications
Clock multiplication
Telecom jitter attenuation
SCL
SDA
ADDR
VSS
XIN
XOUT
XTUNE
VDD
1
2
3
16
15
14
CLKN
CLKP
VDD
FBK
REF
VSS
EXTLF
LOCK/IPRG
FS6131
4
5
6
7
8
13
12
11
10
9
16-pin 0.150" SOIC
Figure 1: Pin Configuration
©2008 SCILLC. All rights reserved.
May 2008 – Rev. 4
Publication Order Number:
FS6131/D
FS6131
LFTC
C
LF
C
LP
XTUNE
(optional)
XCT[3:0],
XLVTEN
Control
ROM
VCXO
Divider
XLROM[2:0]
XLPDEN,
XLSWAP
CRYSTAL LOOP
XLCP[1:0]
XIN
VCXO
XOUT
(optional)
Internal
Loop
Filter
0
EXTLF
STAT[1:0]
1
R
LF
Phase-
Frequency
Detector
UP
EXTLF
(optional)
Charge
Pump
DOWN
Lock
Detect
REFDIV[11:0]
CMOS
1
0
POST3[1:0]
POST2[1:0]
POST1[1:0]
LOCK/
IPRG
(optional)
REF
0
1
REFDSRC
(f
REF
)
Reference
Divider
(N
R
)
MLCP[1:0]
0
PDREF
UP
VCOSPD,
OSCTYPE
GBL
11
1
FBK
1
0
PDFBK
Phase-
Frequency
Detector
Charge
Pump
DOWN
Voltage
Controlled
Oscillator
01
00
10
Clock
Gobbler
OUTMUX[1:0]
Post
Divider
(N
Px
)
CMOS/PECL
Output
CLKP
(f
CLK
)
CLKN
ADDR
Feedback
Divider
(N
F
)
SCL
SDA
I
2
C
Interface
Registers
FBKDIV[13:0]
11
01
10
00
FBKDSRC[1:0]
(f
VCO
)
MAIN LOOP
FS6131
Figure 2: Block Diagram
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down;
DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
DI
DIO
DI
P
AI
AO
AI
P
DIO
AI
P
DI
DI
P
DO
DO
Name
SCL
SDA
ADDR
VSS
XIN
XOUT
XTUNE
VDD
LOCK/IPRG
EXTLF
VSS
REF
FBK
VDD
CLKP
CLKN
Description
Serial interface clock (requires an external pull-up)
Serial interface data input/output (requires an external pull-up)
Address select bit (see Section 5.2.1)
Ground
VCXO feedback
VCXO drive
VCXO tune
Power supply (+5V)
Lock indicator / PECL current drive programming
External loop filter
Ground
Reference frequency input
Feedback input
Power supply (+5V)
Differential clock output (+)
Differential clock output (-)
Rev. 4 | Page 2 of 44 | www.onsemi.com
FS6131
4.0 Functional Block Description
4.1 Main Loop PLL
The main loop phase locked loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in
Error!
Reference source not found.,
the ML-PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an
internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider.
During operation, the reference frequency (f
REF
), generated by either the on-board crystal oscillator or an external frequency source, is
first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus, and is denoted as N
R
for
the reference divider. The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (f
VCO
) through the charge pump and loop filter. The VCO provides a high-speed, low noise,
continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the feedback
divider (the modulus is denoted by N
F
) to close the loop.
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at
the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is
f
VCO
f
=
REF
N
F
N
R
If the VCO frequency is used as the PLL output frequency (f
CLK
) then the basic PLL equation can be rewritten as
⎛
N
⎞
f
CLK
=
f
REF
⎜
F
⎟
⎜
N
⎟
⎝
R
⎠
4.1.1. Reference Divider
The reference divider is designed for low phase jitter. The divider accepts either the output of either the crystal loop (the VCXO output)
or an external reference frequency, and provides a divided-down frequency to the PFD. The reference divider is a 12-bit divider, and
can be programmed for any modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.
4.1.2. Feedback Divider
The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully
programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also
called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO
can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall
power consumption of the divider.
For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective
modulus of the feedback divider path to multiples of eight. The limitation would restrict the ability of the PLL to achieve a desired input-
frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. Large divider
moduli are generally undesirable due to increased phase jitter.
Rev. 4 | Page 3 of 44 | www.onsemi.com
FS6131
f
vco
Dual-
Modulus
Prescaler
M
Counter
A
Counter
Figure 3: Feedback Divider
To understand the operation, refer to
Error! Reference source not found..
The M-counter (with a modulus of M) is cascaded with the
dual-modulus pre-scaler. If the prescaler modulus were fixed at N, the overall modulus of the feedback divider chain would be MXN.
However, the A-counter causes the pre-scaler modulus to be altered to N+1 for the first A outputs of the pre-scaler. The A-counter then
causes the dual-modulus prescaler to revert to a modulus of N until the M-counter reaches its terminal state and resets the entire
divider. The overall modulus can be expressed as
A
(
N
+
1)
+
N
(
M
−
A
)
where M
≥
A, which simplifies to
M
×
N
+
A
4.1.3. Feedback Divider Programming
The requirement that M
≥
A means that the feedback divider can only be programmed for certain values below a divider modulus of 56.
The selection of divider values is listed in Table 2.
If the desired feedback divider is less than 56, find the divider value in the table. Follow the column up to find the A-counter program
value. Follow the row to the left to find the M-counter value.
Above a modulus of 56, the feedback divider can be programmed to any value up to 16383. See both Table 3 and Table 8 for additional
programming information.
Table 2: Feedback Modulus Below 56
M-Counter:
FBKDIV[13:3]
00000000001
00000000010
00000000011
00000000100
00000000101
00000000110
00000000111
A-counter: FBKDIV[2:0]
000
8
16
24
32
40
48
56
001
9
17
25
33
41
49
57
010
-
18
26
34
42
50
58
011
-
-
27
35
43
51
59
100
-
-
-
36
44
52
60
101
-
-
-
-
45
53
61
110
-
-
-
-
-
54
62
111
-
-
-
-
-
-
63
Feedback Divider Modulus
Rev. 4 | Page 4 of 44 | www.onsemi.com
FS6131
4.1.4. Post Divider
The post divider consists of three individually programmable dividers, as shown in
Error! Reference source not found..
POST1[1:0]
POST2[1:0]
POST3[1:0]
f
GBL
Post
Divider 1
(N
P1
)
Post
Divider 2
(N
P2
)
POST DIVIDER (N
Px
)
Post
Divider 3
(N
P3
)
f
out
Figure 4: Post Divider
The moduli of the individual dividers are denoted as N
P1
, N
P2
, and N
P3
, and together they make up the array modulus N
Px
.
N
Px
=
N
P
1
×
N
P
2
×
N
P
3
The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to
the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
⎛
N
⎞⎛
1
⎞
f
CLK
=
f
REF
⎜
F
⎟⎜
⎜
N
⎟⎜
N
⎟
⎟
⎝
R
⎠⎝
Px
⎠
The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies
must be achieved exactly.
Note that a nominal 50/50 duty factor is preserved for selections which have an odd modulus.
4.2 Phase Adjust and Sampling
In line-locked or genlocked applications, it is necessary to know the exact phase relation of the output clock relative to the input clock.
Since the VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input
clock. Every cycle of the input clock equals N
R
/N
F
cycles of the VCO clock.
f
IN
Reference
Divider (N
R
)
Phase
Frequency
Detect
VCO
f
OUT
f
IN
f
OUT
Feedback
Divider (N
F
)
Figure 5: Simple PLL
The addition of a post divider, while adding flexibility, makes the phase relation between the input and output clock unknown because
the post divider is outside the feedback loop.
Rev. 4 | Page 5 of 44 | www.onsemi.com
京公网安备 11010802033920号
EEWORLD
