Freescale Semiconductor
Document Number: MPC8308EC
Rev. 3, 10/2011
MPC8308 PowerQUICC II Pro
Processor Hardware Specification
This document provides an overview of the MPC8308
features and its hardware specifications, including a block
diagram showing the major functional components. The
MPC8308 is a cost-effective, low-power, highly integrated
host processor. The MPC8308 extends the PowerQUICC
family, adding higher CPU performance, additional
functionality, and faster interfaces while addressing the
requirements related to time-to-market, price, power
consumption, and package size.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 2
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ethernet: Three-Speed Ethernet, MII Management . 15
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 25
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 41
Enhanced Secure Digital Host Controller (eSDHC) . 44
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 59
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
System Design Information . . . . . . . . . . . . . . . . . . . 77
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 80
Document Revision History . . . . . . . . . . . . . . . . . . . 82
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Overview
1
Overview
This figure shows the major functional units within the MPC8308. The e300 core in the MPC8308, with
its 16 Kbytes of instruction and 16 Kbytes of data cache, implements the Power Architecture user
instruction set architecture and provides hardware and software debugging support. In addition, the
MPC8308 offers a PCI Express controller, two three-speed 10, 100, 1000 Mbps Ethernet controllers
(eTSEC), a DDR2 SDRAM memory controller, a SerDes block, an enhanced local bus controller (eLBC),
an integrated programmable interrupt controller (IPIC), a general purpose DMA controller, two I
2
C
controllers, dual UART (DUART), GPIOs, USB, general purpose timers, and an SPI controller. The high
level of integration in the MPC8308 helps simplify board design and offers significant bandwidth and
performance.
This figure shows a block diagram of the device.
e300c3 Core with
Power Management
DUART
I2C
Timers
GPIO, SPI
16-Kbyte
I-Cache
Interrupt
Controller
FPU
16-Kbyte
D-Cache
DMA
Enhanced
Local Bus
DDR2
Controller
Enhanced
Secure
Digital Host
Controller
PCI
Express
x1
USB 2.0 HS
Host/Device/OTG
ULPI
eTSEC1
RGMII,MII
eTSEC2
RGMII,MII
Figure 1. MPC8308 Block Diagram
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8308. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
2
Freescale Semiconductor
Electrical Characteristics
2.1.1
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings
1
Characteristic
Symbol
V
DD
AV
DD1,
AV
DD2
GV
DD
NV
DD
Max Value
–0.3 to 1.26
–0.3 to 1.26
–0.3 to 1.9
–0.3 to 3.6
Unit
V
V
V
V
Notes
—
—
—
7
This table lists the absolute maximum ratings.
Core supply voltage
PLL supply voltage
DDR2 DRAM I/O voltage
Local bus, DUART, system control and power management,
eSDHC, I
2
C, USB, Interrupt, Ethernet management, SPI,
Miscellaneous and JTAG I/O voltage
SerDes PHY
XCOREV
DD
,
XPADV
DD
,
SDAV
DD
LV
DD1,
LV
DD2
MV
IN
MV
REF
LV
IN
OV
IN
–0.3 to 1.26
V
—
eTSEC I/O Voltage
Input voltage
DDR2 DRAM signals
DDR2 DRAM reference
eTSEC
Local bus, DUART, system control and power
management, eSDHC, I
2
C, Interrupt,
Ethernet management, SPI, Miscellaneous
and JTAG I/O voltage
Storage temperature range
–0.3 to 2.75 or
–0.3 to 3.6
–0.3 to (GV
DD
+ 0.3)
–0.3 to (GV
DD
+ 0.3)
–0.3 to (LV
DD
+ 0.3)
–0.3 to (NV
DD
+ 0.3)
V
V
V
V
V
6, 8
2, 5
2, 5
4, 5,8
3, 5,7
T
STG
–55 to 150
C
—
Notes:
1. Functional and tested operating conditions are given in
Table 2.
Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2.
Caution:
MV
IN
must not exceed GV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3.
Caution:
OV
IN
must not exceed NV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4.
Caution:
LV
IN
must not exceed LV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
5. (M, L, O)V
IN
and MV
REF
may overshoot/undershoot to a voltage and for a maximum duration as shown in
Figure 2
6. The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode.
7. NV
DD
here refers to NV
DDA
, NV
DDB
,NV
DDG
, NV
DDH
, NV
DDJ
, NV
DDP_K
from the ball map.
8. LV
DD1
here refers to NV
DDC
and LV
DD2
refers to NV
DDF
from the ball map
2.1.2
Power Supply Voltage Specification
This table provides the recommended operating conditions for the device. Note that the values in this table
are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
3
Electrical Characteristics
Table 2. Recommended Operating Conditions
Characteristic
SerDes internal digital power
SerDes internal digital power
SerDes I/O digital power
SerDes analog power for PLL
SerDes analog power for PLL
SerDes I/O digital power
Core supply voltage
Analog supply for e300 core APLL
2
Analog supply for system APLL
2
DDR2 DRAM I/O voltage
Differential reference voltage for DDR controller
Standard I/O voltage (Local bus, DUART, system control and power
management, eSDHC, USB, I
2
C, Interrupt, Ethernet management,
SPI, Miscellaneous and JTAG I/O voltage)
3
eTSEC IO supply
4,5
Analog and digital ground
Operating temperature range
6
Notes:
1
2
3
4
5
6
Symbol
XCOREV
DD
XCOREV
SS
XPADV
DD
SDAV
DD
SDAV
SS
XPADV
SS
V
DD
AV
DD1
AV
DD2
GV
DD
MV
REF
NV
DD
Recommended Value
1
1.0 V ± 50 mV
0.0
1.0 V ± 50 mV
1.0 V ± 50 mV
0
0
1.0 V ± 50 mV
1.0 V ± 50 mV
1.0 V ± 50 mV
1.8 V ± 100 mV
GVDD/2 (0.49
GV
DD
to
0.51
GV
DD
)
3.3 V ± 300 mV
Unit
V
V
V
V
V
V
V
V
V
V
V
V
LV
DD1
, LV
DD2
V
SS
T
A
/T
J
2.5 V ± 125 mV
3.3 V ± 300 mV
0.0
Standard = 0 to 105
Extended = -40 to 105
V
V
C
GV
DD
, NV
DD
, AV
DD
, and V
DD
must track each other and must vary in the same direction—either in the positive or negative
direction.
This voltage is the input to the filter discussed in
Section 23.2, “PLL Power Supply Filtering,”
and not necessarily the voltage
at the AV
DD
pin, which may be reduced from V
DD
by the filter.
NV
DD
here refers to NV
DDA
, NV
DDB
,NV
DDG
, NV
DDH
, NV
DDJ
and NV
DDP_K
from the ball map.
The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode.
LV
DD1
here refers to NV
DDC
and LV
DD2
refers to NV
DDF
from the ball map.
Minimum temperature is specified with T
A
; Maximum temperature is specified with T
J.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
4
Freescale Semiconductor
Electrical Characteristics
This figure shows the undershoot and overshoot voltages at the interfaces of the device.
G/L/NV
DD
+ 20%
G/L/NV
DD
+ 5%
V
IH
G/L/NV
DD
VSS
VSS – 0.3 V
V
IL
VSS – 0.7 V
Not to Exceed 10%
of t
interface1
Note:
1. t
interface
refers to the clock period associated with the bus clock interface.
Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD
2.1.3
Output Driver Characteristics
Table 3. Output Drive Capability
Driver Type
Output Impedance ()
42
18
42
42
Supply Voltage
NV
DD
= 3.3 V
GV
DD
= 1.8 V
NV
DD
= 3.3 V
LV
DD
= 2.5/3.3 V
This table provides information on the characteristics of the output driver strengths.
Local bus interface utilities signals
DDR2 signals
1
DUART, system control, I
2
C, JTAG, eSDHC, GPIO,SPI, USB
eTSEC signals
1
Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR).
For more information, see the
MPC8308 PowerQUICC II Pro Processor Reference Manual.
2.1.4
Power Sequencing
It is required to apply the core supply voltage (V
DD
) before the I/O supply voltages (GV
DD
, LV
DD
, and
NV
DD
) and assert PORESET before the power supplies fully ramp up. The core voltage supply must rise
to 90% of its nominal value before the I/O supplies reach 0.7 V; see
Figure 3.
If this recommendation is not observed and I/O voltages are supplied before the core voltage, there might
be a period of time that all input and output pins are actively driven and cause contention and excessive
current. To overcome side effects of this condition, the application environment may require tuning of
external pull-up or pull-down resistors on particular signals to lesser values.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
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