a
FEATURES
Two 8-Bit DACs In One Package
20-Lead DIP/SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer
Rail-to-Rail Operation
Low Power Operation 3 mA max @ 3.3 V
Power-Down to 1 A max @ 25 C
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
2.7 V to 5.5 V, Parallel Input
Dual Voltage Output 8-Bit DAC
AD7302
FUNCTIONAL BLOCK DIAGRAM
AD7302
INPUT
REGISTER
DAC
REGISTER
I DAC A
I/V
V
OUT
A
D7
D0
A/B
WR
CS
INPUT
REGISTER
DAC
REGISTER
I DAC B
I/V
V
OUT
B
CONTROL
LOGIC
MUX
POWER ON
RESET
÷2
AGND
PD
CLR
LDAC
REFIN
V
DD
DGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7302 is a dual, 8-bit voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision
output buffers allow the DAC outputs to swing rail to rail. The
AD7302 has a parallel microprocessor and DSP-compatible
interface with high speed registers and double buffered interface
logic. Data is loaded to the registers on the rising edge of
CS
or
WR
and the
A/B
pin selects either DAC A or DAC B.
Reference selection for AD7302 can be either an internal
reference derived from the V
DD
or an external reference applied
at the REFIN pin. Both DACs can be simultaneously updated
using the asynchronous
LDAC
input and can be cleared by
using the asynchronous
CLR
input.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump-
tion is less than 10 mW at 3.3 V, reducing to 3
µW
in power-
down mode.
The AD7302 is available in a 20-pin plastic dual-in-line package,
20-lead SOIC and a 20-lead TSSOP package.
1. Low Power, Single Supply Operation. This part operates
from a single +2.7 V to +5.5 V supply and typically consumes
15 mW at 5 V, making it ideal for battery powered applications.
2. The on-chip output buffer amplifiers allow the outputs of the
DACs to swing rail to rail with a settling time of typically 1.2
µs.
3. Internal or external reference capability.
4. High speed parallel interface.
5. Power-Down Capability. When powered down the DAC
consumes less than 1
µA
at 25°C.
6. Packaged in 20-lead DIP, SOIC and TSSOP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD7302–SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Zero Code Error @ 25°C
Gain Error
3
Zero Code Temperature Coefficient
DAC REFERENCE INPUT
REFIN Input Range
REFIN Input Impedance
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Digital to Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DC Output Impedance
Short Circuit Current
Power Supply Rejection Ratio
4
LOGIC INPUTS
Input Current
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
V
DD
I
DD
V
DD
= 3.3 V
@ 25°C
@ T
MIN
to T
MAX
V
DD
= 5.5 V
@ 25°C
@ T
MIN
to T
MAX
I
DD
(Full Power-Down)
@ 25°C
T
MIN
to T
MAX
8
±
1
±
1
–0.75
3
±
1
100
(V
DD
= +2.7 V to +5.5 V, Internal Reference; C
L
= 100 pF, R
L
= 10 k
to T
MAX
unless otherwise noted)
Units
Bits
LSB max
LSB max
LSB typ
LSB typ
% FSR typ
µV/°C
typ
V min to max
MΩ typ
V min to max
µs
max
V/µs typ
nV-s typ
nV-s typ
nV-s typ
LSB typ
Ω
typ
mA typ
%/% max
µA
max
V max
V max
V min
V min
pF max
V min/max
Conditions/Comments
to V
DD
and GND;
B Versions
1
Note 2
Guaranteed Monotonic
All Zeroes Loaded to DAC Register
1.0 to V
DD
/2
10
0 to V
DD
2
7.5
1
0.2
0.2
±
0.2
40
14
0.0003
±
10
0.8
0.6
2.4
2.1
7
2.7/5.5
Typically 1.2
µs
1 LSB Change Around Major Carry
∆V
DD
=
±
10%
V
DD
= +5 V
V
DD
= +3 V
V
DD
= +5 V
V
DD
= +3 V
2.8
3
4.5
5
1
2
mA max
mA max
mA max
mA max
µA
max
µA
max
Both DACs Active and Excluding Load Currents
V
IH
= V
DD
and V
IL
= GND
Typically 2.3 mA
See Figures 6 and 7
V
IH
= V
DD
and V
IL
= GND
Typically 2.8 mA
See Figures 6 and 7
V
IH
= V
DD
and V
IL
= GND
See Figure 18
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +105°C.
2
Relative Accuracy is calculated using a reduced code range of 15 to 245.
3
Gain error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4
Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
–2–
REV. 0
AD7302
TIMING CHARACTERISTICS
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
0
0
0
0
20
15
4.5
20
20
20
1, 2
(V
DD
= +2.7 V to +5.5 V; GND = 0 V; Reference = Internal V
DD
/2 Reference;
all specifications T
MIN
to T
MAX
unless otherwise noted)
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
Address to Write Setup Time
Address Valid to Write Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
Data Setup Time
Data Hold Time
Write to
LDAC
Setup Time
LDAC
Pulse Width
CLR
Pulse Width
Limit at T
MIN
, T
MAX
(B Version)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
(V
IL
+ V
IH
)/2. tr and tf should not exceed 1
µs
on any digital input.
2
See Figure 1.
t
1
A/B
t
2
CS
t
3
t
4
t
5
WR
t
6
D7–D0
t
7
t
8
LDAC
t
9
CLR
t
10
Figure 1. Timing Diagram for Parallel Data Write
REV. 0
–3–
AD7302
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Reference Input Voltage to AGND . . . .–0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 0.3 V
V
OUT
A, V
OUT
B to AGND . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 900 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 102°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 700 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7302 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
AD7302BN
AD7302BR
AD7302BRU
Temperature
Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package
Options*
N-20
R-20
RU-20
*N = Plastic DIP; R = Small Outline; RU =Thin Shrink Small Outline.
–4–
REV. 0
AD7302
PIN FUNCTION DESCRIPTIONS
Pin
No.
1-8
9
10
11
12
13
Mnemonic Function
D7–D0
CS
WR
A/B
PD
LDAC
Parallel Data Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of
CS
and
WR.
Chip Select. Active low logic input.
Write Input.
WR
is an active low logic input used in conjunction with
CS
and
A/B
to write data to the selected
DAC register.
DAC Select. Address pin used to select writing to either DAC A or DAC B.
Active low input used to put the part into low power mode reducing current consumption to less than 1
µA.
Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with
the contents of their DAC registers. If
LDAC
is permanently tied low, the DACs are updated on the rising
edge of
WR.
Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all
zeroes and the DAC outputs are cleared to zero volts.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND.
External Reference Input. This can used as the reference for both DACs. The range on this reference input is
1 V to V
DD
/2. If REFIN is directly tied to V
DD
the internal V
DD
/2 reference is selected.
Analog Ground reference point and return point for all analog current on the part.
Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output.
Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output.
Digital Ground reference point and return point for all digital current on the part.
PIN CONFIGURATION
14
15
16
17
18
19
20
CLR
V
DD
REFIN
AGND
V
OUT
B
V
OUT
A
DGND
(MSB) DB7 1
DB6 2
DB5 3
DB4 4
DB3 5
DB2 6
20 DGND
19 V
OUT
A
18 V
OUT
B
17 AGND
AD7302
16 REFIN
TOP VIEW 15 V
DD
(Not to Scale)
DB1 7
14
CLR
(LSB) DB0 8
CS
9
WR
10
13
LDAC
12
PD
11
A/B
REV. 0
–5–
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