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74LVX174MTCX

Description
IC D-type pos trg sngl 16tssop
Categorylogic    logic   
File Size78KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVX174MTCX Overview

IC D-type pos trg sngl 16tssop

74LVX174MTCX Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP16,.25
Contacts16
Reach Compliance Codeunknown
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup55000000 Hz
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of digits6
Number of functions1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup14.5 ns
propagation delay (tpd)21 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width4.4 mm
minfmax95 MHz
Base Number Matches1
74LVX174 Low Voltage Hex D-Type Flip-Flop with Master Reset
May 1993
Revised October 2003
74LVX174
Low Voltage Hex D-Type Flip-Flop with Master Reset
General Description
The LVX174 is a high-speed hex D flip-flop. The device is
used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to storage
during the LOW-to-HIGH clock transition. The device has a
Master Reset to simultaneously clear all flip-flops.
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX174M
74LVX174SJ
74LVX174MTC
Package Number
M16A
M16D
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
5
CP
MR
Q
0
–Q
5
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
© 2003 Fairchild Semiconductor Corporation
DS011607
www.fairchildsemi.com

74LVX174MTCX Related Products

74LVX174MTCX 74LVX174SJX 74LVX174MX
Description IC D-type pos trg sngl 16tssop IC D-type pos trg sngl 16sop IC D-type pos trg sngl 16soic
Is it Rohs certified? conform to conform to conform to
Maker Fairchild Fairchild Fairchild
Parts packaging code TSSOP SOIC SOIC
package instruction TSSOP, TSSOP16,.25 SOP, SOP16,.3 SOP, SOP16,.25
Contacts 16 16 16
Reach Compliance Code unknown compliant unknown
series LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e3 e3 e3
length 5 mm 10.1 mm 9.9 mm
Load capacitance (CL) 50 pF 50 pF 50 pF
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
Maximum Frequency@Nom-Sup 55000000 Hz 55000000 Hz 55000000 Hz
MaximumI(ol) 0.004 A 0.004 A 0.004 A
Humidity sensitivity level 1 1 1
Number of digits 6 6 6
Number of functions 1 1 1
Number of terminals 16 16 16
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Output polarity TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SOP SOP
Encapsulate equivalent code TSSOP16,.25 SOP16,.3 SOP16,.25
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE
method of packing TAPE AND REEL TAPE AND REEL TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260 260
power supply 3.3 V 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 14.5 ns 14.5 ns 14.5 ns
propagation delay (tpd) 21 ns 21 ns 21 ns
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 2.1 mm 1.75 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2 V 2 V 2 V
Nominal supply voltage (Vsup) 2.7 V 2.7 V 2.7 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) MATTE TIN Matte Tin (Sn)
Terminal form GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 4.4 mm 5.3 mm 3.9 mm
minfmax 95 MHz 95 MHz 95 MHz
Base Number Matches 1 1 1
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