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74LVX374SJX

Description
IC D-type pos trg sngl 20sop
Categorylogic    logic   
File Size92KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVX374SJX Overview

IC D-type pos trg sngl 20sop

74LVX374SJX Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP20,.3
Contacts20
Reach Compliance Codecompliant
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length12.6 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
Maximum Frequency@Nom-Sup55000000 Hz
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup16 ns
propagation delay (tpd)23 ns
Certification statusNot Qualified
Maximum seat height2.1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width5.3 mm
74LVX374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
October 1993
Revised April 2005
74LVX374
Low Voltage Octal D-Type Flip-Flop with
3-STATE Outputs
General Description
The LVX374 is a high-speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flip-
flops. The inputs tolerate up to 7V allowing interface of 5V
systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX374M
74LVX374SJ
74LVX374MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Description
© 2005 Fairchild Semiconductor Corporation
DS011612
www.fairchildsemi.com

74LVX374SJX Related Products

74LVX374SJX 74LVX374MX
Description IC D-type pos trg sngl 20sop IC D-type pos trg sngl 20soic
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker Fairchild Fairchild
Parts packaging code SOIC SOIC
package instruction SOP, SOP20,.3 SOP, SOP20,.4
Contacts 20 20
Reach Compliance Code compliant compliant
series LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 code R-PDSO-G20 R-PDSO-G20
JESD-609 code e3 e3
length 12.6 mm 12.8015 mm
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type BUS DRIVER BUS DRIVER
Maximum Frequency@Nom-Sup 55000000 Hz 55000000 Hz
MaximumI(ol) 0.004 A 0.004 A
Humidity sensitivity level 1 1
Number of digits 8 8
Number of functions 1 1
Number of ports 2 2
Number of terminals 20 20
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Output characteristics 3-STATE 3-STATE
Output polarity TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP
Encapsulate equivalent code SOP20,.3 SOP20,.4
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE
method of packing TAPE AND REEL TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 16 ns 16 ns
propagation delay (tpd) 23 ns 23 ns
Certification status Not Qualified Not Qualified
Maximum seat height 2.1 mm 2.642 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2 V 2 V
Nominal supply voltage (Vsup) 2.7 V 2.7 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED 30
Trigger type POSITIVE EDGE POSITIVE EDGE
width 5.3 mm 7.493 mm
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