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74VCX32500GX

Description
txrx 36bit univ bus 114fbga
Categorylogic    logic   
File Size147KB,9 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

74VCX32500GX Overview

txrx 36bit univ bus 114fbga

74VCX32500GX Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeBGA
package instructionLFBGA, BGA114,6X19,32
Contacts114
Reach Compliance Codecompliant
Control typeINDEPENDENT CONTROL
Counting directionBIDIRECTIONAL
seriesALVC/VCX/A
JESD-30 codeR-PBGA-B114
JESD-609 codee0
length16 mm
Load capacitance (CL)30 pF
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
MaximumI(ol)0.024 A
Humidity sensitivity level3
Number of digits36
Number of functions1
Number of ports2
Number of terminals114
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Encapsulate equivalent codeBGA114,6X19,32
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup2.7 ns
propagation delay (tpd)19.6 ns
Certification statusNot Qualified
Maximum seat height1.4 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.4 V
Nominal supply voltage (Vsup)1.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
translateN/A
Trigger typeNEGATIVE EDGE
width5.5 mm
Base Number Matches1
74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
March 2001
Revised August 2003
74VCX32500
Low Voltage 36-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32500 is an 36-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
The VCX32500 is designed for low voltage (1.4V to 3.6V)
V
CC
applications with I/O capability up to 3.6V.
The 74VCX32500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Note 1:
To ensure the high-impedance state during power up or power
down, OEBA should be tied to V
CC
through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
Features
s
1.4V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(A to B, B to A)
2.9 ns max for 3.0V to 3.6V V
CC
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
±
24 mA @ 3.0V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latchup performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number
74VCX32500G
(Note 2)(Note 3)
Package Number
BGA114A
Package Description
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2:
Ordering Code “G” indicates Trays.
Note 3:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2003 Fairchild Semiconductor Corporation
DS500403
www.fairchildsemi.com

74VCX32500GX Related Products

74VCX32500GX
Description txrx 36bit univ bus 114fbga
Is it Rohs certified? incompatible
Maker Fairchild
Parts packaging code BGA
package instruction LFBGA, BGA114,6X19,32
Contacts 114
Reach Compliance Code compliant
Control type INDEPENDENT CONTROL
Counting direction BIDIRECTIONAL
series ALVC/VCX/A
JESD-30 code R-PBGA-B114
JESD-609 code e0
length 16 mm
Load capacitance (CL) 30 pF
Logic integrated circuit type REGISTERED BUS TRANSCEIVER
MaximumI(ol) 0.024 A
Humidity sensitivity level 3
Number of digits 36
Number of functions 1
Number of ports 2
Number of terminals 114
Maximum operating temperature 85 °C
Minimum operating temperature -40 °C
Output characteristics 3-STATE
Output polarity TRUE
Package body material PLASTIC/EPOXY
encapsulated code LFBGA
Encapsulate equivalent code BGA114,6X19,32
Package shape RECTANGULAR
Package form GRID ARRAY, LOW PROFILE, FINE PITCH
method of packing TAPE AND REEL
Peak Reflow Temperature (Celsius) 260
power supply 3.3 V
Prop。Delay @ Nom-Sup 2.7 ns
propagation delay (tpd) 19.6 ns
Certification status Not Qualified
Maximum seat height 1.4 mm
Maximum supply voltage (Vsup) 3.6 V
Minimum supply voltage (Vsup) 1.4 V
Nominal supply voltage (Vsup) 1.5 V
surface mount YES
technology CMOS
Temperature level INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb)
Terminal form BALL
Terminal pitch 0.8 mm
Terminal location BOTTOM
Maximum time at peak reflow temperature NOT SPECIFIED
translate N/A
Trigger type NEGATIVE EDGE
width 5.5 mm
Base Number Matches 1

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