Numonyx
TM
StrataFlash
®
Embedded Memory
(P33-65nm)
256-Mbit, 512-Mbit (256M/256M)
Datasheet
Product Features
High performance:
— 95ns initial access time for Easy BGA
— 105ns initial access time for TSOP
— 25ns 16-word asynchronous-page read
mode
— 52MHz with zero wait states, 17ns clock-to-
data output synchronous-burst read mode
— 4-, 8-, 16-, and continuous-word options
for burst mode
— Buffered Enhanced Factory Programming at
2.0MByte/s (typ) using 512-word buffer
— 3.0V buffered programming at 1.5MByte/s
(Typ) using 512-word buffer
Architecture:
— Multi-Level Cell Technology: Highest
Density at Lowest Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte main blocks
— Blank Check to verify an erase block
Voltage and Power:
— V
CC
(core) voltage: 2.3 V – 3.6 V
— V
CCQ
(I/O) voltage: 2.3 V – 3.6 V
— Standby current: 65uA (Typ) for 256-Mbit
— Continuous synchronous read current: 21
mA (Typ)/24 mA (Max) at 52 MHz
Security:
— One-Time Programmable Registers:
— 64 unique factory device identifier bits
— 2112 user-programmable OTP bits
—
—
—
—
—
Absolute write protection: V
PP
= V
SS
Power-transition erase/program lockout
Individual zero-latency block locking
Individual block lock-down capability
Password Access feature
Software:
— 20µs (Typ) program suspend
— 20µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Function
Interface Command Set compatible
— Common Flash Interface capable
Density and Packaging
— 56-Lead TSOP package (256-Mbit only)
— 64-Ball Easy BGA package (256, 512-Mbit)
— 16-bit wide data bus
Quality and Reliability
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— 65nm ETOX™ X process technology
Datasheet
1
Aug 2009
Order Number: 320003-08
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at
http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx, B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009, Numonyx, B.V., All Rights Reserved.
Datasheet
2
Aug 2009
Order Number: 320003-08
P33-65nm
Contents
1.0
Functional Description
............................................................................................... 5
1.1
Introduction ....................................................................................................... 5
1.2
Overview ........................................................................................................... 5
1.3
Virtual Chip Enable Description.............................................................................. 6
1.4
Memory Maps ..................................................................................................... 7
Package Information
................................................................................................. 8
2.1
56-Lead TSOP..................................................................................................... 8
2.2
64-Ball Easy BGA Package .................................................................................... 9
Ballouts
................................................................................................................... 11
Signals
.................................................................................................................... 13
4.1
Dual-Die Configurations ..................................................................................... 14
Bus Operations
........................................................................................................ 15
5.1
Read ............................................................................................................... 15
5.2
Write ............................................................................................................... 15
5.3
Output Disable .................................................................................................. 15
5.4
Standby ........................................................................................................... 16
5.5
Reset............................................................................................................... 16
Command Set
.......................................................................................................... 17
6.1
Device Command Codes ..................................................................................... 17
6.2
Device Command Bus Cycles .............................................................................. 18
Read
7.1
7.2
7.3
7.4
Operation........................................................................................................
21
Asynchronous Page-Mode Read ........................................................................... 21
Synchronous Burst-Mode Read............................................................................ 21
Read Device Identifier........................................................................................ 22
Read CFI .......................................................................................................... 22
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Program Operation
.................................................................................................. 23
8.1
Word Programming ........................................................................................... 23
8.2
Buffered Programming ....................................................................................... 23
8.3
Buffered Enhanced Factory Programming.............................................................. 24
8.4
Program Suspend .............................................................................................. 26
8.5
Program Resume............................................................................................... 27
8.6
Program Protection............................................................................................ 27
Erase Operation.......................................................................................................
28
9.1
Block Erase ...................................................................................................... 28
9.2
Blank Check ..................................................................................................... 28
9.3
Erase Suspend .................................................................................................. 29
9.4
Erase Resume................................................................................................... 29
9.5
Erase Protection ................................................................................................ 29
9.0
10.0 Security
................................................................................................................... 30
10.1 Block Locking.................................................................................................... 30
10.2 Selectable OTP Blocks ........................................................................................ 32
10.3 Password Access ............................................................................................... 32
11.0 Status Register........................................................................................................
33
11.1 Read Configuration Register................................................................................ 34
11.2 One-Time Programmable (OTP) Registers ............................................................. 40
12.0 Power and Reset Specifications
............................................................................... 43
Datasheet
3
Aug 2009
Order Number: 320003-08
P33-65nm
12.1
12.2
12.3
Power-Up and Power-Down .................................................................................43
Reset Specifications ...........................................................................................43
Power Supply Decoupling....................................................................................44
13.0 Maximum Ratings and Operating Conditions
............................................................45
13.1 Absolute Maximum Ratings .................................................................................45
13.2 Operating Conditions..........................................................................................45
14.0 Electrical Specifications
...........................................................................................46
14.1 DC Current Characteristics ..................................................................................46
14.2 DC Voltage Characteristics ..................................................................................47
15.0 AC Characteristics
....................................................................................................48
15.1 AC Test Conditions.............................................................................................48
15.2 Capacitance ......................................................................................................49
15.3 AC Read Specifications .......................................................................................49
15.4 AC Write Specifications .......................................................................................54
15.5 Program and Erase Characteristics .......................................................................58
16.0 Ordering Information...............................................................................................59
16.1 Discrete Products...............................................................................................59
16.2 SCSP Products...................................................................................................60
A
Supplemental Reference Information.......................................................................61
A.1
Common Flash Interface .....................................................................................61
A.2
Flowcharts ........................................................................................................73
A.3
Write State Machine ...........................................................................................83
Conventions - Additional Documentation
.................................................................87
B.1
Acronyms .........................................................................................................87
B.2
Definitions and Terms ........................................................................................87
Revision History.......................................................................................................89
B
C
Datasheet
4
Aug 2009
Order Number: 320003-08
P33-65nm
1.0
1.1
Functional Description
Introduction
This document provides information about the Numonyx
TM
StrataFlash
®
Embedded
Memory (P33-65nm) device and describes its features, operations, and specifications.
P33-65nm is the latest generation of Numonyx
TM
StrataFlash
®
Embedded Memory
(P33-65nm) devices. P33-65nm device will be offered in 64-Mbit up through 2-Gbit
densities. This document covers specifically 256-Mbit and 512-Mbit (256M/256M)
product information. Benefits include more density in less space, high-speed interface
NOR device, and support for code and data storage. Features include high-performance
synchronous-burst read mode, fast asynchronous access times, low power, flexible
security options, and two industry-standard package choices.
P33-65nm is manufactured using Numonyx™ 65nm ETOX™ X process technology.
1.2
Overview
This family of devices provides high performance at low voltage on a 16-bit data bus.
Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power-up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the RCR enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal.
A WAIT signal provides an easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast factory program and erase operations. Designed for low-
voltage systems, the P33 Family Flash memory supports read operations with VCC at
3.0V, and erase and program operations with VPP at 3.0V or 9.0V. Buffered Enhanced
Factory Programming provides the fastest flash array programming performance with
VPP at 9.0V, which increases factory throughput. With VPP at 3.0V, VCC and VPP can be
tied together for a simple, ultra low power design. In addition to voltage flexibility, a
dedicated VPP connection provides complete data protection when VPP
≤
V
PPLK
.
The Command User Interface is the interface between the system processor and all
internal operations of the device. An internal Write State Machine automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
The P33 Family Flash memory one-time-programmable (OTP) register allows unique
flash device identification that can be used to increase system security. The individual
Block Lock feature provides zero-latency block locking and unlocking. The P33-65nm
device adds enhanced protection via Password Access Mode which allows user to
protect write and/or read access to the defined blocks. In addition, the P33 Family
Flash memory may also provide the backward compatible OTP permanent lock feature.
Datasheet
5
Aug 2009
Order Number:320003-08
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