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DS187 (v1.20.1) July 2, 2018
Product Specification
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Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
Table 1:
Absolute Maximum Ratings
(1)
(Cont’d)
Symbol
V
IN(3)(4)(5)
V
CCBATT
V
MGTAVCC
V
MGTAVTT
V
MGTREFCLK
V
IN
I
DCIN-FLOAT
I
DCIN-MGTAVTT
I
DCIN-GND
I
DCOUT-FLOAT
I
DCOUT-MGTAVTT
XADC
V
CCADC
V
REFP
Temperature
T
STG
T
SOL
T
j
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Applies to both MIO supply banks V
CCO_MIO0
and V
CCO_MIO1
.
The lower absolute voltage specification always applies.
For I/O operation, refer to the
7 Series FPGAs SelectIO Resources User Guide
(UG471) or the
Zynq-7000 SoC Technical Reference Manual
(UG585).
The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see
Table 4.
See
Table 11
for TMDS_33 specifications.
For soldering guidelines and thermal considerations, see the
Zynq-7000 SoC Packaging and Pinout Specification
(UG865).
Description
I/O input voltage for HR I/O banks
I/O input voltage (when V
CCO
= 3.3V) for V
REF
and differential I/O standards
except TMDS_33
(6)
Key memory battery backup supply
Min
–0.40
–0.40
–0.5
Max
V
CCO
+ 0.55
2.625
2.0
Units
V
V
V
GTP Transceiver (XC7Z015 Only)
Analog supply voltage for the GTP transmitter and receiver circuits
Analog supply voltage for the GTP transmitter and receiver termination
circuits
Reference clock absolute input voltage
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
DC input current for receiver input pins DC coupled RX termination = floating
DC input current for receiver input pins DC coupled RX
termination = V
MGTAVTT
DC input current for receiver input pins DC coupled RX termination = GND
DC output current for transmitter pins DC coupled RX termination = floating
DC output current for transmitter pins DC coupled RX
termination = V
MGTAVTT
XADC supply relative to GNDADC
XADC reference input relative to GNDADC
–0.5
–0.5
–0.5
–0.5
–
–
–
–
–
1.1
1.32
1.32
1.26
14
12
6.5
14
12
V
V
V
V
mA
mA
mA
mA
mA
–0.5
–0.5
2.0
2.0
V
V
Storage temperature (ambient)
Maximum soldering temperature for Pb/Sn component bodies
(7)
Maximum soldering temperature for Pb-free component bodies
(7)
Maximum junction temperature
(7)
–65
–
–
–
150
+220
+260
+125
°C
°C
°C
°C
2.
3.
4.
5.
6.
7.
Table 2:
Recommended Operating Conditions
(1)(2)
Symbol
PS
V
CCPINT
V
CCPAUX
V
CCPLL
V
CCO_DDR
V
CCO_MIO(3)
PS internal logic supply voltage
PS auxiliary supply voltage
PS PLL supply
PS DDR I/O supply voltage
PS MIO I/O supply voltage for MIO banks
0.95
1.71
1.71
1.14
1.71
1.00
1.80
1.80
–
–
1.05
1.89
1.89
1.89
3.465
V
V
V
V
V
Description
Min
Typ
Max
Units
DS187 (v1.20.1) July 2, 2018
Product Specification
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Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
Table 2:
Recommended Operating Conditions
(1)(2)
(Cont’d)
Symbol
V
PIN(4)
PL
V
CCINT(5)
V
CCAUX
V
CCBRAM(5)
V
CCO(6)(7)
V
IN(4)
I
IN(9)
V
CCBATT(10)
V
MGTAVCC(11)
V
MGTAVTT(11)
XADC
V
CCADC
V
REFP
Temperature
Junction temperature operating range for commercial (C) temperature
devices
Junction temperature operating range for extended (E) temperature
devices
Junction temperature operating range for industrial (I) temperature
devices
Junction temperature operating range for expanded (Q) temperature
devices
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
All voltages are relative to ground. The PL and PS share a common ground.
For the design of the power distribution system consult the
Zynq-7000 SoC PCB Design Guide
(UG933).
Applies to both MIO supply banks V
CCO_MIO0
and V
CCO_MIO1
.
The lower absolute voltage specification always applies.
V
CCINT
and V
CCBRAM
should be connected to the same supply.
Configuration data is retained even if V
CCO
drops to 0V.
Includes V
CCO
of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%.
See
Table 11
for TMDS_33 specifications.
A total of 200 mA per PS or PL bank should not be exceeded.
V
CCBATT
is required only when using bitstream encryption. If battery is not used, connect V
CCBATT
to either ground or V
CCAUX
.
Each voltage listed requires the filter circuit described in the
7 Series FPGAs GTP Transceiver User Guide
(UG482).
Description
PS DDR and MIO I/O input voltage
Min
–0.20
Typ
–
Max
V
CCO_DDR
+ 0.20
V
CCO_MIO
+ 0.20
1.05
0.98
1.89
1.05
0.98
3.465
V
CCO
+ 0.20
2.625
10
1.89
Units
V
PL internal supply voltage
PL -1LI (0.95V) internal supply voltage
PL auxiliary supply voltage
PL block RAM supply voltage
PL -1LI (0.95V) block RAM supply voltage
PL supply voltage for HR I/O banks
I/O input voltage
I/O input voltage (when V
CCO
= 3.3V) for V
REF
and differential I/O
standards except TMDS_33
(8)
Maximum current through any (PS or PL) pin in a powered or unpowered
bank when forward biasing the clamp diode
Battery voltage
0.95
0.92
1.71
0.95
0.92
1.14
–0.20
–0.20
–
1.0
1.00
0.95
1.80
1.00
0.95
–
–
–
–
–
V
V
V
V
V
V
V
V
mA
V
GTP Transceiver (XC7Z015 Only)
Analog supply voltage for the GTP transmitter and receiver circuits
Analog supply voltage for the GTP transmitter and receiver termination
circuits
0.97
1.17
1.0
1.2
1.03
1.23
V
V
XADC supply relative to GNDADC
Externally supplied reference voltage
1.71
1.20
1.80
1.25
1.89
1.30
V
V
0
0
–40
–40
–
–
–
–
85
100
100
125
°C
°C
°C
°C
T
j
DS187 (v1.20.1) July 2, 2018
Product Specification
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Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
Table 3:
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRI
I
REF
I
L
C
IN(2)
C
PIN(2)
Description
Data retention V
CCINT
voltage (below which configuration data might be lost)
Data retention V
CCAUX
voltage (below which configuration data might be lost)
PS_DDR_VREF 0/1, PS_MIO_VREF, and V
REF
leakage current per pin
Input or output leakage current per pin (sample-tested)
PL die input capacitance at the pad
PS die input capacitance at the pad
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 3.3V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 2.5V
Min
0.75
1.5
–
–
–
–
90
68
34
23
12
68
45
–
–
28
35
44
–
–
Typ
(1)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
50
60
1.010
2
Max
–
–
15
15
8
8
330
250
220
150
120
330
180
25
150
55
65
83
–
–
Units
V
V
µA
µA
pF
pF
µA
µA
µA
µA
µA
µA
µA
mA
nA
Ω
Ω
Ω
–
Ω
I
RPU
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.8V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.5V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.2V
Pad pull-down (when selected) @ V
IN
= 3.3V
Pad pull-down (when selected) @ V
IN
= 1.8V
Analog supply current, analog circuits in powered up state
Battery supply current
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_40)
I
RPD
I
CCADC
I
BATT(3)
R
IN_TERM(4)
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_50)
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_60)
n
r
Notes:
1.
2.
3.
4.
Temperature diode ideality factor
Temperature diode series resistance
Typical values are specified at nominal voltage, 25°C.
This measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25°C.
Termination resistance to a V
CCO
/2 level.
DS187 (v1.20.1) July 2, 2018
Product Specification
www.xilinx.com
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4
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
Table 4:
V
IN
Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and PL HR I/O Banks
(1)(2)
AC Voltage Overshoot
% of UI @–40°C to 125°C
AC Voltage Undershoot
–0.40
V
CCO
+ 0.55
100
–0.45
–0.50
–0.55
V
CCO
+ 0.60
V
CCO
+ 0.65
V
CCO
+ 0.70
V
CCO
+ 0.75
V
CCO
+ 0.80
V
CCO
+ 0.85
V
CCO
+ 0.90
V
CCO
+ 0.95
Notes:
1.
2.
A total of 200 mA per bank should not be exceeded.
The peak voltage of the overshoot or undershoot, and the duration above V
CCO
+ 0.20V or below GND –0.20V, must not exceed the values
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