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74LVQ02SJX

Description
IC gate nor 4ch 2-inp 14-soic
Categorylogic    logic   
File Size48KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVQ02SJX Overview

IC gate nor 4ch 2-inp 14-soic

74LVQ02SJX Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP14,.3
Contacts14
Reach Compliance Codecompliant
seriesLVQ
JESD-30 codeR-PDSO-G14
JESD-609 codee3
length10.2 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNOR GATE
MaximumI(ol)0.012 A
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup8 ns
propagation delay (tpd)12 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height2.1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width5.3 mm
Base Number Matches1
74LVQ02 Low Voltage Quad 2-Input NOR Gate
February 1992
Revised June 2001
74LVQ02
Low Voltage Quad 2-Input NOR Gate
General Description
The LVQ02 contains four 2-input NOR gates.
Features
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Guaranteed incident wave switching into 75
Ordering Code:
Order Number
74LVQ02SC
74LVQ02SJ
Package Number
M14A
M14D
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation
DS011342
www.fairchildsemi.com

74LVQ02SJX Related Products

74LVQ02SJX 74LVQ02SCX
Description IC gate nor 4ch 2-inp 14-soic IC gate nor 4ch 2-inp 14-soic
Is it Rohs certified? conform to conform to
Maker Fairchild Fairchild
Parts packaging code SOIC SOIC
package instruction SOP, SOP14,.3 SOP, SOP14,.25
Contacts 14 14
Reach Compliance Code compliant unknown
series LVQ LVQ
JESD-30 code R-PDSO-G14 R-PDSO-G14
JESD-609 code e3 e3
length 10.2 mm 8.65 mm
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type NOR GATE NOR GATE
MaximumI(ol) 0.012 A 0.012 A
Humidity sensitivity level 1 1
Number of functions 4 4
Number of entries 2 2
Number of terminals 14 14
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP
Encapsulate equivalent code SOP14,.3 SOP14,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE
method of packing TAPE AND REEL TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 8 ns 8 ns
propagation delay (tpd) 12 ns 12 ns
Certification status Not Qualified Not Qualified
Schmitt trigger NO NO
Maximum seat height 2.1 mm 1.75 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2 V 2 V
Nominal supply voltage (Vsup) 2.7 V 2.7 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 5.3 mm 3.9 mm
Base Number Matches 1 1
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