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DS191 (v1.18.1) July 2, 2018
Product Specification
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1
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
Table 1:
Absolute Maximum Ratings
(1)
(Cont’d)
Symbol
V
REF
Input reference voltage
I/O input voltage for HR I/O banks
V
IN(3)(4)(5)
I/O input voltage for HP I/O banks
I/O input voltage (when V
CCO
= 3.3V) for V
REF
and differential I/O standards
except TMDS_33
(6)
V
CCBATT
V
MGTAVCC
V
MGTAVTT
V
MGTVCCAUX
V
MGTREFCLK
V
MGTAVTTRCAL
V
IN
I
DCIN-FLOAT
I
DCIN-MGTAVTT
I
DCIN-GND
I
DCOUT-FLOAT
Key memory battery backup supply
Description
Min
–0.5
–0.40
–0.55
–0.40
–0.5
Max
2.0
V
CCO
+ 0.55
V
CCO
+ 0.55
2.625
2.0
Units
V
V
V
V
V
GTX Transceiver
Analog supply voltage for the GTX transmitter and receiver circuits
Analog supply voltage for the GTX transmitter and receiver termination circuits
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers
GTX transceiver reference clock absolute input voltage
Analog supply voltage for the resistor calibration circuit of the GTX transceiver
column
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
DC input current for receiver input pins DC coupled RX termination = floating
DC input current for receiver input pins DC coupled RX termination = V
MGTAVTT
DC input current for receiver input pins DC coupled RX termination = GND
DC output current for transmitter pins DC coupled RX termination = floating
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–
–
–
–
–
1.1
1.32
1.935
1.32
1.32
1.26
14
12
6.5
14
12
V
V
V
V
V
V
mA
mA
mA
mA
mA
I
DCOUT-MGTAVTT
DC output current for transmitter pins DC coupled RX termination = V
MGTAVTT
XADC
V
CCADC
V
REFP
XADC supply relative to GNDADC
XADC reference input relative to GNDADC
–0.5
–0.5
2.0
2.0
V
V
Temperature
T
STG
T
SOL
T
j
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Applies to both MIO supply banks V
CCO_MIO0
and V
CCO_MIO1
.
The lower absolute voltage specification always applies.
For I/O operation, refer to the
7 Series FPGAs SelectIO Resources User Guide
(UG471) or the
Zynq-7000 SoC Technical Reference Manual
(UG585).
The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see
Table 4
and
Table 5.
See
Table 12
for TMDS_33 specifications.
For soldering guidelines and thermal considerations, see the
Zynq-7000 SoC Packaging and Pinout Specification
(UG865).
Storage temperature (ambient)
Maximum soldering temperature for Pb/Sn component bodies
(7)
Maximum soldering temperature for Pb-free component bodies
(7)
Maximum junction temperature
(7)
–65
–
–
–
150
+220
+260
+125
°C
°C
°C
°C
2.
3.
4.
5.
6.
7.
DS191 (v1.18.1) July 2, 2018
Product Specification
www.xilinx.com
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2
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
Table 2:
Recommended Operating Conditions
(1)(2)
Symbol
PS
V
CCPINT(3)
V
CCPAUX
V
CCPLL
V
CCO_DDR
V
CCO_MIO(4)
V
PIN(5)
PS internal logic supply voltage
PS auxiliary supply voltage
PS PLL supply voltage
PS DDR supply voltage
PS supply voltage for MIO banks
PS DDR and MIO I/O input voltage
0.95
1.71
1.71
1.14
1.71
–0.20
1.00
1.80
1.80
–
–
–
1.05
1.89
1.89
1.89
3.465
V
CCO_DDR
+ 0.20
V
CCO_MIO
+ 0.20
1.03
0.97
1.03
0.97
1.89
3.465
1.89
1.89
2.06
V
CCO
+ 0.20
2.625
10
1.89
V
V
V
V
V
V
Description
Min
Typ
Max
Units
PL
V
CCINT(6)
V
CCBRAM(6)
V
CCAUX
V
CCO(7)(8)
V
CCAUX_IO(9)
PL internal supply voltage
PL -2LI (0.95V) internal supply voltage
PL block RAM supply voltage
PL -2LI (0.95V) block RAM supply voltage
PL auxiliary supply voltage
PL supply voltage for HR I/O banks
PL supply voltage for HP I/O banks
PL auxiliary supply voltage when set to 1.8V
PL auxiliary supply voltage when set to 2.0V
I/O input voltage
V
IN(5)
I
IN(11)
V
CCBATT(12)
I/O input voltage (when V
CCO
= 3.3V) for V
REF
and differential
I/O standards except TMDS_33
(10)
Maximum current through any (PS or PL) pin in a powered or
unpowered bank when forward biasing the clamp diode
Battery voltage
0.97
0.93
0.97
0.93
1.71
1.14
1.14
1.71
1.94
–0.20
–0.20
–
1.0
1.00
0.95
1.00
0.95
1.80
–
–
1.80
2.00
–
–
–
–
V
V
V
V
V
V
V
V
V
V
V
mA
V
GTX Transceiver
Analog supply voltage for the GTX transceiver QPLL frequency
range
≤
10.3125 GHz
(14)(15)
Analog supply voltage for the GTX transceiver QPLL frequency
range > 10.3125 GHz
Analog supply voltage for the GTX transmitter and receiver
termination circuits
Auxiliary analog QPLL voltage supply for the transceivers
Analog supply voltage for the resistor calibration circuit of the
GTX transceiver column
0.97
1.02
1.17
1.75
1.17
1.0
1.05
1.2
1.80
1.2
1.08
1.08
1.23
1.85
1.23
V
V
V
V
V
MGTAVCC
(13)
V
MGTAVTT(13)
V
MGTVCCAUX(13)
V
MGTAVTTRCAL(13)
XADC
V
CCADC
V
REFP
XADC supply relative to GNDADC
Externally supplied reference voltage
1.71
1.20
1.80
1.25
1.89
1.30
V
V
DS191 (v1.18.1) July 2, 2018
Product Specification
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Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
Table 2:
Recommended Operating Conditions
(1)(2)
(Cont’d)
Symbol
Temperature
Junction temperature operating range for commercial (C)
temperature devices
Junction temperature operating range for extended (E)
temperature devices
Junction temperature operating range for industrial (I)
temperature devices
Junction temperature operating range for expanded (Q)
temperature devices
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
All voltages are relative to ground. The PL and PS share a common ground.
For the design of the power distribution system consult the
Zynq-7000 SoC PCB Design Guide
(UG933).
When the processor cores operate F
CPU_6X4X_621_MAX
at 1 GHz (-3E speed grade) or when the DDR interface operates at 1333 Mb/s, the
V
CCPINT
minimum is 0.97V and the V
CCPINT
maximum is 1.03V.
Applies to both MIO supply banks V
CCO_MIO0
and V
CCO_MIO1
.
The lower absolute voltage specification always applies.
V
CCINT
and V
CCBRAM
should be connected to the same supply.
Configuration data is retained even if V
CCO
drops to 0V.
Includes V
CCO
of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), and 3.3V (HR I/O only) at ±5%.
For more information, refer to the V
CCAUX_IO
section of the
7 Series FPGAs SelectIO Resources User Guide
(UG471) or the
Zynq-7000 SoC
Technical Reference Manual
(UG585).
See
Table 12
for TMDS_33 specifications.
A total of 200 mA per PS or PL bank should not be exceeded.
V
CCBATT
is required only when using bitstream encryption. If battery is not used, connect V
CCBATT
to either ground or V
CCAUX
.
Each voltage listed requires the filter circuit described in the
7 Series FPGAs GTX/GTH Transceivers User Guide
(UG476).
For data rates
≤
10.3125 Gb/s, V
MGTAVCC
should be 1.0V ±3% for lower power consumption.
For lower power consumption, V
MGTAVCC
should be 1.0V ±3% over the entire CPLL frequency range.
Description
Min
Typ
Max
Units
0
0
–40
–40
–
–
–
–
85
100
100
125
°C
°C
°C
°C
T
j
DS191 (v1.18.1) July 2, 2018
Product Specification
www.xilinx.com
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4
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
Table 3:
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRI
I
REF
I
L
C
IN(2)
C
PIN(2)
Description
Data retention V
CCINT
voltage (below which configuration data might be lost)
Data retention V
CCAUX
voltage (below which configuration data might be lost)
PS_DDR_VREF 0/1, PS_MIO_VREF, and V
REF
leakage current per pin
Input or output leakage current per pin (sample-tested)
PL die input capacitance at the pad
PS die input capacitance at the pad
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 3.3V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 2.5V
Min
0.75
1.5
–
–
–
–
90
68
34
23
12
68
45
–
–
28
35
44
–
–
Typ
(1)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
50
60
1.010
2
Max
–
–
15
15
8
8
330
250
220
150
120
330
180
25
150
55
65
83
–
–
Units
V
V
µA
µA
pF
pF
µA
µA
µA
µA
µA
µA
µA
mA
nA
Ω
Ω
Ω
–
Ω
I
RPU
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.8V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.5V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.2V
Pad pull-down (when selected) @ V
IN
= 3.3V
Pad pull-down (when selected) @ V
IN
= 1.8V
Analog supply current, analog circuits in powered up state
Battery supply current
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_40)
I
RPD
I
CCADC
I
BATT(3)
R
IN_TERM(4)
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_50)
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_60)
n
r
Notes:
1.
2.
3.
4.
Temperature diode ideality factor
Temperature diode series resistance
Typical values are specified at nominal voltage, 25°C.
This measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25°C.
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