A1440A-1PL84I datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> A1440A-1PL84I

A1440A-1PL84I: DescriptionIC fpga 70 I/O 84plcc; CategoryProgrammable logic devices Programmable logic; File Size4MB，90 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

A1440A-1PL84I Overview

IC fpga 70 I/O 84plcc

A1440A-1PL84I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
package instruction	QCCJ, LDCC84,1.2SQ
Reach Compliance Code	compliant
Other features	MAX 70 I/OS
maximum clock frequency	150 MHz
Combined latency of CLB-Max	2.6 ns
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
length	29.3116 mm
Humidity sensitivity level	3
Configurable number of logic blocks	564
Equivalent number of gates	4000
Number of entries	140
Number of logical units	564
Output times	140
Number of terminals	84
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	564 CLBS, 4000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	29.3116 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Revision 3

Accelerator Series FPGAs – ACT 3 Family

Features

• Up to 10,000 Gate Array Equivalent Gates (up to 25,000

equivalent PLD Gates)

• Highly Predictable Performance with 100% Automatic Place-

and-Route

• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)

• Up to 186 MHz On-Chip Performance (–1 Speed Grade)

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock Networks

Table 1 • ACT 3 Family Product Information

Device

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Package (40 gates)

20-Pin PAL Equivalent Packages (100 gates)

Logic Modules

S-Module

C-Module

Dedicated Flip-Flops

User I/Os (maximum)

Chip-to-Chip

(MHz)

Accumulators (16-bit, MHz)

Loadable Counter (16-bit, MHz)

Prescaled Loadable Counters (16-bit, MHz)

Datapath, Shift Registers (MHz)

Clock-to-Output (pad-to-pad, ns)

Packages

(by pin count)

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

CQFP

PG100

PL84

PQ100

–

VQ100

–

PG133

PL84

PQ100, PQ160

–

VQ100

–

CQ132

PG175

PL84

PQ160

–

VQ100

TQ176

–

PG207

–

PQ160, PQ208

–

TQ176

BG225

CQ196

PG257

–

RQ208

–

BG313

CQ256

1,500

3,750

200

104

264

186

9.0

2,500

6,250

310

160

150

360

100

186

9.0

4,000

10,000

100

564

288

276

568

140

186

9.5

6,000

15,000

150

848

432

416

768

168

150

10.0

10,000

25,000

250

100

1,377

697

680

1,153

228

150

10.5

A1415

A1425

A1440

A1460

A14100

•

More than 500 Macro Functions

Replaces up to Twenty 32 Macro-Cell CPLDs

Replaces up to One Hundred 20-Pin PAL

Packages

Up to 1,153 Dedicated Flip-Flops

VQFP, TQFP, BGA, and PQFP Packages

Nonvolatile, User Programmable

Fully Tested Prior to Shipment

5.0 V and 3.3 V Versions

Optimized for Logic Synthesis Methodologies

Low Power CMOS Technology

Maximum Performance

(worst-case commercial, –1 speed grade)

Notes:

1. One flip-flop per S0Module, two flip-flops per I/O Module.

2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1.

3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the

"System Performance Model" on page 1-1

and

Table 1-1 on page 1-2.

4. See the

"Product Plan" table on page III

for package availability.

5. Discontinued device and package combination.

6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product

Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:

PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004

January 2012

Recommended Resources

Lamp driver circuit diagram with short circuit protection

Rotation direction detection circuit

Add dimming function to portable battery lamp

motorcycle battery charger

555 DC wipe circuit changed to AC wipe circuit

Typical circuit of triac controlling three-phase electric heating device

Is there any master who knows about the dot matrix LCD 240128 controller T6963C? Please give me some advice.: I'm using 32F103 MCU to make dot matrix LCD controller, which is T6963C. I'm a novice and I still don't understand it after two days of research. I hope some master can explain it in detail when he ha...; 就是搞 stm32/stm8

DSP assembly feels difficult to start: I am a DSP optimization engineer. I am currently using c66. I want to optimize from the assembly perspective. Can anyone with experience give me some advice? I don't know where to start. The resource ...; 飞哥传输 DSP and ARM Processors

Analysis of the phenomenon of irregular competition in the security industry: With the rapid development of China's economy, various modern hotels, shopping malls, and office buildings stand in the city. These intelligent buildings have higher and higher requirements for securi...; xyh_521 Industrial Control Electronics

ADI Withings Pulse Activity Tracker (Withings Pulse Fitness Tracker): [font=微软雅黑][size=3]Before reading this post, please read this news first [/size][/font][url=https://www.eeworld.com.cn/medical_electronics/2013/1220/article_4335.html][font=微软雅黑][size=3]ADI MEMS makes...; eric_wang Mobile and portable

Common diode rectifier circuit: [p=20, null, left][color=rgb(51, 51, 51)]Rectifier diodes are the most commonly used diodes in diode circuits. The so-called rectifier diode is a diode specially used in power supply circuits to conve...; qwqwqw2088 Analogue and Mixed Signal

avr input capture: #include#include#include #define uchar unsigned char #define uint unsigned int const uchar seg_code[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90,0xff}; uint cap1=0,cap2=0; volatile uchar full_...; 穿行 Microchip MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components