1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
Micron Serial NOR Flash Memory
3V, Multiple I/O, 4KB Sector Erase
N25Q00AA
Features
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Stacked device (four 256Mb die)
SPI-compatible serial bus interface
Double transfer rate (DTR) mode
2.7–3.6V single supply voltage
108 MHz (MAX) clock frequency supported for all
protocols in single transfer rate (STR) mode
54 MHz (MAX) clock frequency supported for all
protocols in DTR mode
Dual/quad I/O instruction provides increased
throughput up to 54 MB/s
Supported protocols
– Extended SPI, dual I/O, and quad I/O
– DTR mode supported on all
Execute-in-place (XIP) mode for all three protocols
– Configurable via volatile or nonvolatile registers
– Enables memory to work in XIP mode directly af-
ter power-on
PROGRAM/ERASE SUSPEND operations
Available protocols
– Available READ operations
– Quad or dual output fast read
– Quad or dual I/O fast read
Flexible to fit application
– Configurable number of dummy cycles
– Output buffer configurable
Software reset
3-byte and 4-byte addressability mode supported
64-byte, user-lockable, one-time programmable
(OTP) dedicated area
Erase capability
– Subsector erase 4KB uniform granularity blocks
– Sector erase 64KB uniform granularity blocks
– Single die erase (32MB)
• Write protection
– Software write protection applicable to every
64KB sector via volatile lock bit
– Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2,
BP3, and TB)
– Additional smart protections, available upon re-
quest
• Electronic signature
– JEDEC-standard 2-byte signature (BA21h)
– Unique ID code (UID): 17 read-only bytes,
including: Two additional extended device ID
bytes to identify device factory options; and cus-
tomized factory data (14 bytes)
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages – JEDEC-standard, all RoHS-compliant
– L-PBGA-24b05/6mm x 8mm ( also known as
LBGA24 )
– SOP2-16/300 mils (also known as SO16W, SO16-
Wide, SOIC-16 )
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PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
Contents
Device Description ........................................................................................................................................... 6
Features ....................................................................................................................................................... 6
3-Byte Address and 4-Byte Address Modes ..................................................................................................... 6
Operating Protocols ...................................................................................................................................... 6
XIP Mode ..................................................................................................................................................... 7
Device Configurability .................................................................................................................................. 7
Signal Assignments ........................................................................................................................................... 8
Signal Descriptions ........................................................................................................................................... 9
Memory Organization .................................................................................................................................... 11
Memory Configuration and Block Diagram .................................................................................................. 11
Memory Map – 1Gb Density ............................................................................................................................ 12
Device Protection ........................................................................................................................................... 13
Serial Peripheral Interface Modes .................................................................................................................... 16
SPI Protocols .................................................................................................................................................. 18
Nonvolatile and Volatile Registers ................................................................................................................... 19
Status Register ............................................................................................................................................ 20
Nonvolatile and Volatile Configuration Registers .......................................................................................... 21
Extended Address Register .......................................................................................................................... 24
Enhanced Volatile Configuration Register .................................................................................................... 25
Flag Status Register ..................................................................................................................................... 26
Command Definitions .................................................................................................................................... 28
READ REGISTER and WRITE REGISTER Operations ........................................................................................ 31
READ STATUS REGISTER or FLAG STATUS REGISTER Command ................................................................ 31
READ NONVOLATILE CONFIGURATION REGISTER Command ................................................................... 32
READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command .................................. 32
READ EXTENDED ADDRESS REGISTER Command ..................................................................................... 33
WRITE STATUS REGISTER Command ......................................................................................................... 33
WRITE NONVOLATILE CONFIGURATION REGISTER Command ................................................................. 34
WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command ................................. 34
WRITE EXTENDED ADDRESS REGISTER Command ................................................................................... 35
READ LOCK REGISTER Command .............................................................................................................. 35
WRITE LOCK REGISTER Command ............................................................................................................ 36
CLEAR FLAG STATUS REGISTER Command ................................................................................................ 37
READ IDENTIFICATION Operations ............................................................................................................... 38
READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 38
READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 39
READ MEMORY Operations ............................................................................................................................ 43
3-Byte Address ........................................................................................................................................... 43
4-Byte Address ........................................................................................................................................... 44
READ MEMORY Operations Timing – Single Transfer Rate ........................................................................... 46
READ MEMORY Operations Timing – Double Transfer Rate ......................................................................... 50
PROGRAM Operations .................................................................................................................................... 54
WRITE Operations .......................................................................................................................................... 59
WRITE ENABLE Command ......................................................................................................................... 59
WRITE DISABLE Command ........................................................................................................................ 59
ERASE Operations .......................................................................................................................................... 61
SUBSECTOR ERASE Command ................................................................................................................... 61
SECTOR ERASE Command ......................................................................................................................... 61
DIE ERASE Command ................................................................................................................................ 62
PROGRAM/ERASE SUSPEND Command ..................................................................................................... 63
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
PROGRAM/ERASE RESUME Command ......................................................................................................
RESET Operations ..........................................................................................................................................
RESET ENABLE and RESET MEMORY Command ........................................................................................
RESET Conditions ......................................................................................................................................
ONE-TIME PROGRAMMABLE Operations .......................................................................................................
READ OTP ARRAY Command ......................................................................................................................
PROGRAM OTP ARRAY Command ..............................................................................................................
ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode .................................................................
ENTER or EXIT 4-BYTE ADDRESS MODE Command ...................................................................................
XIP Mode .......................................................................................................................................................
Activate or Terminate XIP Using Volatile Configuration Register ...................................................................
Activate or Terminate XIP Using Nonvolatile Configuration Register .............................................................
Confirmation Bit Settings Required to Activate or Terminate XIP ..................................................................
Terminating XIP After a Controller and Memory Reset .................................................................................
Power-Up and Power-Down ............................................................................................................................
Power-Up and Power-Down Requirements ..................................................................................................
Power Loss Recovery Sequence ...................................................................................................................
AC Reset Specifications ...................................................................................................................................
Absolute Ratings and Operating Conditions .....................................................................................................
DC Characteristics and Operating Conditions ..................................................................................................
AC Characteristics and Operating Conditions ..................................................................................................
Package Dimensions .......................................................................................................................................
Part Number Ordering Information .................................................................................................................
Revision History .............................................................................................................................................
Rev. M – 03/14 ............................................................................................................................................
Rev. L – 01/14 .............................................................................................................................................
Rev. K – 09/13 .............................................................................................................................................
Rev. J – 07/13 ..............................................................................................................................................
Rev. I – 02/13 ..............................................................................................................................................
Rev. H – 11/12 .............................................................................................................................................
Rev. G – 11/12 .............................................................................................................................................
Rev. F – 06/12 .............................................................................................................................................
Rev. E – 02/12 .............................................................................................................................................
Rev. D – 01/12 .............................................................................................................................................
Rev. C – 11/11 .............................................................................................................................................
Rev. B – 11/11 .............................................................................................................................................
Rev. A – 08/11 .............................................................................................................................................
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PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 7
Figure 2: 24-Ball LBGA (Balls Down) ................................................................................................................. 8
Figure 3: 16-Pin, Plastic Small Outline — SO16 (Top View) ................................................................................ 8
Figure 4: Block Diagram ................................................................................................................................ 11
Figure 5: Bus Master and Memory Devices on the SPI Bus ............................................................................... 17
Figure 6: SPI Modes ....................................................................................................................................... 17
Figure 7: Internal Configuration Register ........................................................................................................ 19
Figure 8: Upper and Lower Memory Array Segments ....................................................................................... 24
Figure 9: READ REGISTER Command ............................................................................................................ 32
Figure 10: WRITE REGISTER Command ......................................................................................................... 34
Figure 11: READ LOCK REGISTER Command ................................................................................................. 36
Figure 12: WRITE LOCK REGISTER Command ............................................................................................... 37
Figure 13: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 39
Figure 14: READ Command ........................................................................................................................... 46
Figure 15: FAST READ Command ................................................................................................................... 46
Figure 16: DUAL OUTPUT FAST READ Command .......................................................................................... 47
Figure 17: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 47
Figure 18: QUAD OUTPUT FAST READ Command ......................................................................................... 48
Figure 19: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 48
Figure 20: FAST READ Command – DTR ......................................................................................................... 50
Figure 21: DUAL OUTPUT FAST READ Command – DTR ................................................................................ 51
Figure 22: DUAL INPUT/OUTPUT FAST READ Command – DTR .................................................................... 51
Figure 23: QUAD OUTPUT FAST READ Command – DTR ............................................................................... 52
Figure 24: QUAD INPUT/OUTPUT FAST READ Command – DTR ................................................................... 52
Figure 25: PAGE PROGRAM Command .......................................................................................................... 55
Figure 26: DUAL INPUT FAST PROGRAM Command ...................................................................................... 56
Figure 27: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 56
Figure 28: QUAD INPUT FAST PROGRAM Command ..................................................................................... 57
Figure 29: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 58
Figure 30: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 60
Figure 31: SUBSECTOR and SECTOR ERASE Command .................................................................................. 62
Figure 32: DIE ERASE Command ................................................................................................................... 63
Figure 33: RESET ENABLE and RESET MEMORY Command ........................................................................... 66
Figure 34: READ OTP Command .................................................................................................................... 67
Figure 35: PROGRAM OTP Command ............................................................................................................ 68
Figure 36: XIP Mode Directly After Power-On .................................................................................................. 71
Figure 37: Power-Up Timing .......................................................................................................................... 73
Figure 38: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 76
Figure 39: Reset Enable ................................................................................................................................. 76
Figure 40: Serial Input Timing ........................................................................................................................ 76
Figure 41: Hold Timing .................................................................................................................................. 77
Figure 42: Output Timing .............................................................................................................................. 77
Figure 43: V
PPH
Timing .................................................................................................................................. 78
Figure 44: AC Timing Input/Output Reference Levels ...................................................................................... 80
Figure 45: L-PBGA-24b05/6mm x 8mm .......................................................................................................... 84
Figure 46: SOP2-16/300 mils .......................................................................................................................... 85
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
List of Tables
Table 1: Signal Descriptions ............................................................................................................................. 9
Table 2: Sectors[2047:0] ................................................................................................................................. 12
Table 3: Data Protection Using Device Protocols ............................................................................................. 13
Table 4: Memory Sector Protection Truth Table .............................................................................................. 13
Table 5: Protected Area Sizes – Upper Area ..................................................................................................... 14
Table 6: Protected Area Sizes – Lower Area ...................................................................................................... 14
Table 7: SPI Modes ........................................................................................................................................ 16
Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ 18
Table 9: Status Register Bit Definitions ........................................................................................................... 20
Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... 21
Table 11: Volatile Configuration Register Bit Definitions .................................................................................. 22
Table 12: Sequence of Bytes During Wrap ....................................................................................................... 23
Table 13: Supported Clock Frequencies – STR ................................................................................................. 23
Table 14: Supported Clock Frequencies – DTR ................................................................................................ 23
Table 15: Extended Address Register Bit Definitions ........................................................................................ 25
Table 16: Enhanced Volatile Configuration Register Bit Definitions .................................................................. 25
Table 17: Flag Status Register Bit Definitions .................................................................................................. 26
Table 18: Command Set ................................................................................................................................. 28
Table 19: Lock Register .................................................................................................................................. 36
Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... 38
Table 21: Read ID Data Out ............................................................................................................................ 38
Table 22: Extended Device ID, First Byte ......................................................................................................... 38
Table 23: Serial Flash Discovery Parameter Data Structure .............................................................................. 40
Table 24: Parameter ID .................................................................................................................................. 40
Table 25: Command/Address/Data Lines for READ MEMORY Commands ....................................................... 43
Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address ............................. 44
Table 27: Data/Address Lines for PROGRAM Commands ................................................................................ 54
Table 28: Suspend Parameters ....................................................................................................................... 64
Table 29: Operations Allowed/Disallowed During Device States ...................................................................... 64
Table 30: Reset Command Set ........................................................................................................................ 66
Table 31: OTP Control Byte (Byte 64) .............................................................................................................. 68
Table 32: XIP Confirmation Bit ....................................................................................................................... 71
Table 33: Effects of Running XIP in Different Protocols .................................................................................... 71
Table 34: Power-Up Timing and V
WI
Threshold ............................................................................................... 74
Table 35: AC RESET Conditions ...................................................................................................................... 75
Table 36: Absolute Ratings ............................................................................................................................. 79
Table 37: Operating Conditions ...................................................................................................................... 79
Table 38: Input/Output Capacitance .............................................................................................................. 79
Table 39: AC Timing Input/Output Conditions ............................................................................................... 80
Table 40: DC Current Characteristics and Operating Conditions ...................................................................... 81
Table 41: DC Voltage Characteristics and Operating Conditions ...................................................................... 81
Table 42: AC Characteristics and Operating Conditions ................................................................................... 82
Table 43: Part Number Information ................................................................................................................ 86
Table 44: Package Details ............................................................................................................................... 87
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
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