®
X9408
Low Noise/Low Power/2-Wire Bus
Data Sheet
January 15, 2009
FN8191.4
Quad Digitally Controlled (XDCP™)
Potentiometers
Description
The X9408 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digital controlled potentiometer is implemented using 63
resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled
by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four Potentiometers in One Package
• 64 Resistor Taps per Potentiometer
• 2-wire Serial Interface
• Wiper Resistance, 40Ω Typical at 5V
• Four Nonvolatile Data Registers for Each Pot
• Nonvolatile Storage of Wiper Position
• Standby Current < 1µA max (Total Package)
• V
CC
= 2.7V to 5.5V Operation
V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V
• 10kΩ, 2.5kΩ End to End Resistances
• High reliability
• Endurance–100,000 Data Changes Per Bit Per Register
• Register Data Retention–100 years
• 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP Packages
• Pb-Free (RoHS Compliant)
Block Diagram
V
CC
V
SS
V+
V-
R0
R1
POT 0
WIPER
COUNTER
REGISTER
(WCR)
V
H0
/R
H0
R0
R1
WIPER
COUNTER
REGISTER
(WCR)
V
H2
/R
H2
WP
SCL
SDA
A0
A1
A2
A3
INTERFACE
AND
CONTROL
CIRCUITRY
DATA
R2
R3
V
L0
/R
L0
V
W0
/R
W0
R2
R3
RESISTOR
ARRAY
POT 2
V
L2
/R
L2
V
W2
/R
W2
8
V
W1
/R
W1
R0
R1
WIPER
COUNTER
REGISTER
(WCR)
V
H1
/R
H1
R0
R1
V
W3
/R
W3
WIPER
COUNTER
REGISTER
(WCR)
V
H3
/R
H3
RESISTOR
ARRAY
POT 1
R2
R3
V
L1
/R
L1
R2
R3
RESISTOR
ARRAY
POT 3
V
L3
/R
L3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9408
Ordering Information
PART NUMBER
X9408YS24*
X9408YS24I*
X9408YV24*
X9408YV24Z* (Note)
X9408YV24I*
X9408YV24IZ* (Note)
X9408WS24*
X9408WS24I*
X9408WV24*
X9408WV24Z* (Note)
X9408WV24I*
X9408WV24IZ* (Note)
X9408YS24-2.7*
X9408YS24I-2.7*
X9408YV24-2.7*
X9408YV24Z-2.7* (Note)
X9408YV24I-2.7*
POTENTIOMETER
ORGANIZATION
(kΩ)
PART MARKING V
CC
LIMITS (V)
X9408YS
X9408YS I
X9408YV
X9408YV Z
X9408YV I
X9408YV Z I
X9408WS
X9408WS I
X9408WV
X9408WV Z
X9408WV I
X9408WV Z I
X9408YS F
X9408YS G
X9408YV F
X9408YV Z F
X9408YV G
2.7 to 5.5
2.5
10
5 ±10%
2.5
TEMP RANGE
(°C)
0 to +70
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
10
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) Tape and Reel
(Pb-Free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-Free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
X9408YV24IZ-2.7T1 (Note) X9408YV Z G
X9408WS24-2.7*
X9408WS24I-2.7*
X9408WS24IZ-2.7* (Note)
X9408WV24-2.7*
X9408WV24Z-2.7* (Note)
X9408WV24I-2.7*
X9408WV24IZ-2.7* (Note)
X9408WS F
X9408WS G
X9408WS Z G
X9408WV F
X9408WV Z F
X9408WV G
X9408WV Z G
*Add "T1" suffix for tape and reel. **Add "T1" suffix for tape and reel.Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8191.4
January 15, 2009
X9408
Pin Descriptions
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the
X9408.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-
ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the guidelines
for calculating typical values on the bus pull-up resistors
graph.
DEVICE ADDRESS (A
0
- A
3
)
The address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input in
order to initiate communication with the X9408. A maximum
of 16 devices may occupy the 2-wire serial bus.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
ANALOG SUPPLIES V+, V-
The Analog Supplies V+, V- are the supply voltages for the
XDCP analog section.
Pin Assignments
SYMBOL
SCL
SDA
A0-A3
DESCRIPTION
Serial Clock
Serial Data
Device Address
V
H0
/R
H0
- V
H3
/R
H3
, V
L0
/R
L0
Potentiometer Pins
(terminal equivalent)
- V
L3
/R
L3
V
W0
/R
W0
- V
W3
/R
W3
WP
V+,V-
V
CC
V
SS
NC
Potentiometer Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
- V
L3
/R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
/R
W
(V
W0
/R
W0
– V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Pinouts
X9408
(24 LD DIP/SOIC)
TOP VIEW
V
CC
1
V
L0
/R
L0
2
V
H0
/R
H0
3
V
W0
/R
W0
4
A
2
5
WP 6
SDA 7
A
1
8
V
L1
/R
L1
9
V
H1
/R
H1
10
V
W1
/R
W1
11
V
SS
12
24 V+
23 V
L3
/R
L3
22 V
H3
/R
H3
21 V
W3
/R/R
H1
20 A
0
19 NC
18 A
3
17 SCL
16 V
L2
/R
L2
15 V
H2
/R
H2
14 V
W2
/R
W2
13 V-
X9408
(24 LD TSSOP)
TOP VIEW
SDA 1
A
1
2
V
L1
/R
L1
3
V
H1
/R
H1
4
V
W1
/R
W1
5
V
SS
6
V- 7
V
W2
/R
W2
8
V
H2
/R
H2
9
V
L2
/R
L2
10
SCL 11
A
3
12
24 WP
23 A
2
22 V
W0
/R
W0
21 V
H0
/R
H0
20 V
L0
/R
L0
19 V
CC
18 V+
17 V
L3
/R
L3
16 V
H3
/R
H3
15 V
W3
/R
W3
14 A
0
13 NC
3
FN8191.4
January 15, 2009
X9408
Principals of Operation
The X9408 is a highly integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the XDCP
potentiometers.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
W
)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The six bits of the WCR are
decoded to select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Serial Interface
The X9408 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9408 will be
considered a slave device in all applications.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier (refer
to Figure 1 below). For the X9408 this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
LOW
). SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.
0
1
0
1
A3
A2
A1
A0
Start Condition
All commands to the X9408 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
HIGH
). The X9408 continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
DEVICE ADDRESS
FIGURE 1. SLAVE ADDRESS
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9408 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9408 will
respond with a final acknowledge.
The next four bits of the slave address are the device
address. The physical device address is defined by the state
of the A
0
- A
3
inputs. The X9408 compares the serial data
stream with the address input state; a successful compare of
all four address bits is required for the X9408 to respond with
an acknowledge. The A
0
- A
3
inputs can be actively driven
by CMOS input signals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal Nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command
the X9408 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the X9408
is still busy with the write operation no ACK will be returned.
If the X9408 has completed the write operation an ACK will
be returned and the master can then proceed with the next
operation.
Array Description
The X9408 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R
H
and
R
L
inputs).
4
FN8191.4
January 15, 2009
X9408
Flow 1. ACK Polling Sequence
NON-VOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
REGISTER
SELECT
I3
I2
I1
I0
R1
R0
P1
P0
INSTRUCTIONS
ISSUE
START
WIPER COUNTER
REGISTER SELECT
FIGURE 2. INSTRUCTION BYTE FORMAT
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
RETURNED?
YES
NO
The four high order bits define the instruction. The next two
bits (R1 and R0) select one of the four registers that is to be
acted upon when a register oriented instruction is issued.
The last bits (P1, P0) select which one of the four
potentiometers is to be affected by the instruction.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the Data
Registers. A transfer from a Data Register to a Wiper
Counter Register is essentially a write to a static RAM. The
response of the wiper to this action will be delayed t
WRL
. A
transfer from the Wiper Counter Register (current wiper
position), to a data register is a write to nonvolatile memory
and takes a minimum of t
WR
to complete. The transfer can
occur between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein the
transfer occurs between all of the potentiometers and one of
their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9408; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are: Read Wiper Counter Register (read
the current wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents of the
selected nonvolatile register) and Write Data Register (write
a new value to the selected Data Register). The sequence of
operations is shown in Figure 4.
FURTHER
OPERATION?
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
Instruction Structure
The next byte sent to the X9408 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of the two pots
and when applicable they point to one of four associated
registers. The format is shown in Figure 2.
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
P1
P0
A
C
K
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
5
FN8191.4
January 15, 2009
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