EEWORLDEEWORLDEEWORLD

Part Number

Search

IDT71V35761SA183BQI8

Description
IC sram 4.5mbit 183mhz 165cabga
Categorystorage   
File Size326KB,21 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

IDT71V35761SA183BQI8 Overview

IC sram 4.5mbit 183mhz 165cabga

128K x 36
IDT71V35761YS/S
3.3V Synchronous SRAMs
IDT71V35761YSA/SA
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
Features
128K x 36 memory configurations
Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Description
The IDT71V35761 are high-speed SRAMs organized as
128K x 36. The IDT71V35761 SRAMs contain write, data, address and
control registers. Internal logic allows the SRAM to generate a self-timed
write based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the
LBO
input pin.
The IDT71V35761 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
Pin Description Summary
A
0
-A
17
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
CLK
ADV
ADSC
ADSP
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
N/A
5301 tbl 01
1
©2010 Integrated Device Technology, Inc.
MAY 2010
DSC-5301/05
I don't know if it counts as a benefit. LIS3DHTR
This model was cleared out of the warehouse and 1397 pieces were sold. The original plate is gone. The original belt has not been touched. DC is 18+ See if anyone here has any use for it. Each is 4.5 ...
深圳诺伊斯电子 Buy&Sell
【TI Video】 Overview of the Triple-Channel Step-Down Power Management Unit LM10524
[i=s]This post was last edited by dontium on 2015-1-23 11:47[/i] TI application engineer Dubocanin introduces TI's three-way buck power management unit LM10524 designed for solid-state drive applicati...
德州仪器_视频 Analogue and Mixed Signal
Help!!!
I'm a newbie and would like to ask all the developers: I've learned theoretical courses such as circuit principles and single-chip microcomputers in school, but I don't know how to apply them at all.....
dr17 Embedded System
Analysis of typical circuits in the RF part of mobile phones
Without pictures, there is no truth. Let me show you the whole picture first:[b]File download[/b]:...
幸福的娃 RF/Wirelessly
Show off the event prizes - backpack
It's still an activity of TI University Program. Thanks to TI and the hard-working EE administrators. Thank you:victory:The quality is still great~ There are various pockets and zippers (I liked schoo...
sunduoze Talking
DS1302 outputs all 0xff. What's going on?
DS1302 outputs all 0xff. What's going on? My source code is as follows #include typedef unsigned char uchar; typedef unsigned int uint; /**************Macro definition****************/ #define DS_RST ...
tpcore Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1427  1635  2761  2767  1351  29  33  56  28  31 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号