XS1-L8A-64-LQ64 Datasheet
2015/04/14
XMOS © 2015, All Rights Reserved
Document Number: X4912,
XS1-L8A-64-LQ64 Datasheet
1
Table of Contents
1
xCORE Multicore Microcontrollers
.
2
XS1-L8A-64-LQ64 Features
. . . . .
3
Pin Configuration
. . . . . . . . . .
4
Signal Description
. . . . . . . . . .
5
Product Overview
. . . . . . . . . .
6
PLL
. . . . . . . . . . . . . . . . . . .
7
Boot Procedure
. . . . . . . . . . . .
8
Memory
. . . . . . . . . . . . . . . .
9
JTAG
. . . . . . . . . . . . . . . . . .
10 Board Integration
. . . . . . . . . .
11 DC and Switching Characteristics
.
12 Package Information
. . . . . . . .
13 Ordering Information
. . . . . . . .
Appendices
. . . . . . . . . . . . . . . . .
A
Configuration of the XS1
. . . . . .
B
Processor Status Configuration
. .
C
Tile Configuration
. . . . . . . . . .
D
Node Configuration
. . . . . . . . .
E
XMOS USB Interface
. . . . . . . . .
F
Device Errata
. . . . . . . . . . . . .
G
JTAG, xSCOPE and Debugging
. . .
H
Schematics Design Check List
. . .
I
PCB Layout Design Check List
. . .
J
Associated Design Documentation
K
Related Documentation
. . . . . . .
L
Revision History
. . . . . . . . . . .
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37
45
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TO OUR VALUED CUSTOMERS
It is our intention to provide you with accurate and comprehensive documentation for the hardware and
software components used in this product. To subscribe to receive updates, visit
http://www.xmos.com/.
XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you “AS IS” with
no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the information, or any particular implementation thereof, is or will be free from any
claims of infringement and again, shall have no liability in relation to any such claims.
XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries,
and may not be used without written permission. Company and product names mentioned in this document
are the trademarks or registered trademarks of their respective owners.
X4912,
XS1-L8A-64-LQ64
XS1-L8A-64-LQ64 Datasheet
2
1 xCORE Multicore Microcontrollers
The XS1-L Series is a comprehensive range of 32-bit multicore microcontrollers
that brings the low latency and timing determinism of the xCORE architecture to
mainstream embedded applications. Unlike conventional microcontrollers, xCORE
multicore microcontrollers execute multiple real-time tasks simultaneously and
communicate between tasks using a high speed network. Because xCORE multicore
microcontrollers are completely deterministic, you can write software to implement
functions that traditionally require dedicated hardware.
PLL
Security
OTP ROM
xTIME: schedulers
timers, clocks
SRAM
64KB
JTAG
debug
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
PLL
Security
OTP ROM
xTIME: schedulers
timers, clocks
SRAM
64KB
JTAG
debug
xCONNECT
channels, links
xCONNECT
channels, links
I/O Pins
Hardware
response
ports
xCORE logical core
Figure 1:
XS1-L Series:
4-16 core
devices
Key features of the XS1-L8A-64-LQ64 include:
Tiles:
Devices consist of one or more xCORE tiles. Each tile contains between
four and eight 32-bit xCOREs with highly integrated I/O and on-chip memory.
Logical cores
Each logical core can execute tasks such as computational code,
DSP code, control software (including logic decisions and executing a state
machine) or software that handles I/O. Section
5.1
xTIME scheduler
The xTIME scheduler performs functions similar to an RTOS,
in hardware. It services and synchronizes events in a core, so there is no
requirement for interrupt handler routines. The xTIME scheduler triggers cores
on events generated by hardware resources such as the I/O pins, communication
channels and timers. Once triggered, a core runs independently and concurrently
to other cores, until it pauses to wait for more events. Section
5.2
X4912,
I/O Pins
Hardware
response
ports
xCORE logical core
XS1-L8A-64-LQ64
XS1-L8A-64-LQ64 Datasheet
3
Channels and channel ends
Tasks running on logical cores communicate using
channels formed between two channel ends. Data can be passed synchronously
or asynchronously between the channel ends assigned to the communicating
tasks. Section
5.5
xCONNECT Switch and Links
Between tiles, channel communications are im-
plemented over a high performance network of xCONNECT Links and routed
through a hardware xCONNECT Switch. Section
5.6
Ports
The I/O pins are connected to the processing cores by Hardware Response
ports. The port logic can drive its pins high and low, or it can sample the value
on its pins optionally waiting for a particular condition. Section
5.3
Clock blocks
xCORE devices include a set of programmable clock blocks that
can be used to govern the rate at which ports execute. Section
5.4
Memory
Each xCORE Tile integrates a bank of SRAM for instructions and data,
and a block of one-time programmable (OTP) memory that can be configured for
system wide security features. Section
8
PLL
The PLL is used to create a high-speed processor clock given a low speed
external oscillator. Section
6
JTAG
The JTAG module can be used for loading programs, boundary scan testing,
in-circuit source-level debugging and programming the OTP memory. Section
9
1.1
Software
Devices are programmed using C, C++ or xC (C with multicore extensions). XMOS
provides tested and proven software libraries, which allow you to quickly add
interface and processor functionality such as USB, Ethernet, PWM, graphics driver,
and audio EQ to your applications.
1.2
xTIMEcomposer Studio
The xTIMEcomposer Studio development environment provides all the tools you
need to write and debug your programs, profile your application, and write images
into flash memory or OTP memory on the device. Because xCORE devices oper-
ate deterministically, they can be simulated like hardware within xTIMEcomposer:
uniquely in the embedded world, xTIMEcomposer Studio therefore includes a static
timing analyzer, cycle-accurate simulator, and high-speed in-circuit instrumenta-
tion.
xTIMEcomposer can be driven from either a graphical development environment,
or the command line. The tools are supported on Windows, Linux and MacOS X
and available at no cost from
xmos.com/downloads.
Information on using the
tools is provided in the xTIMEcomposer User Guide,
X3766.
X4912,
XS1-L8A-64-LQ64
XS1-L8A-64-LQ64 Datasheet
4
2 XS1-L8A-64-LQ64 Features
Multicore Microcontroller with Advanced Multi-Core RISC Architecture
•
Eight real-time logical cores
•
Core share up to 500 MIPS
•
Each logical core has:
— Guaranteed throughput of between
1
/
4
and
1
/
8
of tile MIPS
— 16x32bit dedicated registers
•
159 high-density 16/32-bit instructions
— All have single clock-cycle execution (except for divide)
— 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic
functions
Programmable I/O
•
36 general-purpose I/O pins, configurable as input or output
— Up to 16 x 1bit port, 5 x 4bit port, 2 x 8bit port, 1 x 16bit port
— 2 xCONNECT links
•
Port sampling rates of up to 60 MHz with respect to an external clock
•
32 channel ends for communication with other cores, on or off-chip
Memory
•
64KB internal single-cycle SRAM for code and data storage
•
8KB internal OTP for application boot code
Hardware resources
•
6 clock blocks
•
10 timers
•
4 locks
JTAG Module for On-Chip Debug
Security Features
•
Programming lock disables debug and prevents read-back of memory contents
•
AES bootloader ensures secrecy of IP held on external flash memory
Ambient Temperature Range
•
Commercial qualification: 0 °C to 70 °C
•
Industrial qualification: -40 °C to 85 °C
Speed Grade
•
5: 500 MIPS
•
4: 400 MIPS
Power Consumption
•
Active Mode
— 200 mA at 500 MHz (typical)
— 160 mA at 400 MHz (typical)
•
Standby Mode
— 14 mA
64-pin LQFP package 0.5 mm pitch
X4912,
XS1-L8A-64-LQ64
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