DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter
June 2007
DM74AS161, Synchronous 4-Bit Counter with
Asynchronous Clear
DM74AS163, Synchronous 4-Bit Counter
Features
■
Switching specifications at 50pF
■
Switching specifications guaranteed over full
■
Synchronously programmable
■
Internal look ahead for fast counting
■
Carry output for n-bit cascading
■
Synchronous counting
■
Load control line
■
ESD inputs
tm
temperature and V
CC
range
■
Advanced oxide-isolated, ion-implanted Schottky TTL
process
■
Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
■
Improved AC performance over Schottky and low
power Schottky counterparts
General Description
These synchronous presettable counters feature an
internal carry look ahead for application in high speed
counting designs. The DM74AS161 and DM74AS163
are 4-bit binary counters. The DM74AS161 clear asyn-
chronously, while the DM74AS163 clear synchronously.
The carry output is decoded to prevent spikes during
normal counting mode of operation. Synchronous
operation is provided by having all flip-flops clocked
simultaneously so that outputs change coincident with
each other when so instructed by count enable inputs
and internal gating. This mode of operation eliminates
the output counting spikes which are normally associ-
ated with asynchronous (ripple clock) counters. A buff-
ered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
These counters are fully programmable, that is, the out-
puts may each be preset to either level. As presetting is
synchronous, setting up a low level at the LOAD input
disables the counter and causes the outputs to agree
with set up data after the next clock pulse regardless of
the levels of enable input. LOW-to-HIGH transitions at
the LOAD input are perfectly acceptable regardless of
the logic levels on the clock or enable inputs.
The DM74AS161 clear function is asynchronous. A low
level at the clear input sets all four of the flip-flop outputs
LOW regardless of the levels of clock, load or enable
inputs. This counter is provided with a clear on power-up
feature. The DM74AS163 clear function is synchronous;
and a low level at the clear input sets all four of the flip-
flop outputs LOW after the next clock pulse, regardless
of the levels of enable inputs. This synchronous clear
allows the count length to be modified easily, as decod-
ing the maximum count desired can be accomplished
with one external NAND gate. The gate output is con-
nected to the clear input to synchronously clear the
counter to all LOW outputs. LOW-to-HIGH transitions at
the clear input of the DM74AS163 is also permissible
regardless of the levels of logic on the clock, enable or
load inputs.
The carry look ahead circuitry provides for cascading
counters for n bit synchronous application without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs (P and T) and a ripple carry
output. Both count-enable inputs must be HIGH to count.
The T input is fed forward to enable the ripple carry out-
put. The ripple carry output thus enabled will produce a
high level output pulse with a duration approximately
equal to the high level portion of QA output. This high
level overflow ripple carry pulse can be used to enable
successive cascaded stages. HIGH-to-LOW level transi-
tions at the enable P or T inputs of the DM74AS161 and
DM74AS163, may occur regardless of the logic level on
the clock.
The DM74AS161 and DM74AS163 feature a fully inde-
pendent clock circuit. Changes made to control inputs
(enable P or T, or load) that will modify the operating
mode will have no effect until clocking occurs. The func-
tion of the counter (whether enabled, disabled, loading
or counting) will be dictated solely by the conditions
meeting the stable set-up and hold times.
©1984 Fairchild Semiconductor Corporation
DM74AS161, DM74AS163 Rev. 1.2
www.fairchildsemi.com
DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
T
A
T
STG
θ
JA
Supply Voltage
Input Voltage
Parameter
Rating
7V
7V
0°C to +70°C
–65°C to +150°C
101.0°C/W
Operating Free Air Temperature Range
Storage Temperature Range
Typical Thermal Resistance
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
t
SU
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Parameter
Min.
4.5
2
Nom.
5
Max.
5.5
0.8
–2
20
Units
V
V
V
mA
mA
MHz
ns
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
t
SETUP
, Set-Up Time
Data; A, B, C, D
En P, En T
LOAD
LOW
CLEAR
(Only for DM74AS163) HIGH
Set-up 1 (Only for DM74AS161) CLEAR
0
8
8
8
12
9
8
0
0
0
0
0
6.7
8
75
t
H
t
HOLD
, Hold Time
Data; A, B, C, D
En P, En T
LOAD
CLEAR
(Only for DM74AS163)
ns
Hold 0 (Only for DM74AS161)
t
WCLK
t
WCLR
Width of Clock Pulse
CLEAR
ns
ns
Width of Clear Pulse, (DM74ASAS161 LOW)
©1984 Fairchild Semiconductor Corporation
DM74AS161, DM74AS163 Rev. 1.2
www.fairchildsemi.com
5
京公网安备 11010802033920号
EEWORLD
