54F 74F374 Octal D-Type Flip-Flop with TRI-STATE Outputs
May 1995
54F 74F374
Octal D-Type Flip-Flop with TRI-STATE Outputs
General Description
The ’F374 is a high-speed low-power octal D-type flip-flop
featuring separate D-type inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications A buff-
ered Clock (CP) and Output Enable (OE) are common to all
flip-flops
Features
Y
Y
Y
Y
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
TRI-STATE outputs for bus-oriented applications
Guaranteed 4000V minimum ESD protection
Commercial
74F374PC
Military
Package
Number
N20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Molded Shrink Small Outline EIAJ Type II
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F374DM (QB)
74F374SC (Note 1)
74F374SJ (Note 1)
74F374MSA (Note 1)
54F374FM (QB)
54F374LM (QB)
J20A
M20B
M20D
MSA20
W20A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX SJX and MSAX
Logic Symbols
Connection Diagrams
Pin Assignment for DIP
SOIC SSOP and Flatpak
Pin Assignment
for LCC
TL F 9524–1
IEEE IEC
TL F 9524 – 3
TL F 9524 – 2
TL F 9524–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9524
RRD-B30M75 Printed in U S A
Unit Loading Fan Out
Pin
Names
D
0
– D
7
CP
OE
O
0
– O
7
54F 74F
Description
UL
HIGH LOW
Input I
IH
I
IL
Output I
OH
I
OL
Data Inputs
10 10
20
mA
b
0 6 mA
Clock Pulse Input (Active Rising Edge)
10 10
20
mA
b
0 6 mA
TRI-STATE Output Enable Input (Active LOW)
10 10
20
mA
b
0 6 mA
b
3 mA 24 mA (20 mA)
TRI-STATE Outputs
150 40 (33 3)
Functional Description
The ’F374 consists of eight edge-triggered flip-flops with in-
dividual D-type inputs and TRI-STATE true outputs The
buffered clock and buffered Output Enable are common to
all flip-flops The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH Clock (CP) transition With
the Output Enable (OE) LOW the contents of the eight flip-
flops are available at the outputs When the OE is HIGH the
outputs go to the high impedance state Operation of the
OE input does not affected the state of the flip-flops
Truth Table
Inputs
D
n
H
L
X
CP
L
L
X
OE
L
L
H
Internal
Register
H
L
X
Output
O
n
H
L
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
L
e
LOW-to-HIGH Clock Transition
Logic Diagram
TL F 9524 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
b
65 C to
a
150 C
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
ESD Last Passing Voltage (Min)
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
30 mA to
a
5 0 mA
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
b
0 5V to V
CC
Standard Output
b
0 5V to
a
5 5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
54F 10% V
CC
54F 10% V
CC
74F 10% V
CC
74F 10% V
CC
74F 5% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
74F
74F
4 75
3 75
b
0 6
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
Min
I
IN
e b
18 mA
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
e
e
e
e
e
e
b
1 mA
b
3 mA
b
1 mA
b
3 mA
b
1 mA
b
3 mA
25
24
25
24
27
27
05
05
20 0
50
100
70
250
50
V
Min
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCZ
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
V
mA
mA
mA
V
mA
mA
mA
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
Max
0 0V
Max
I
OL
e
20 mA
I
OL
e
24 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V
V
OUT
e
2 7V
V
OUT
e
0 5V
V
OUT
e
0V
V
OUT
e
5 25V
V
O
e
HIGH Z
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
55
b
60
50
b
50
b
150
500
86
3
AC Electrical Characteristics
74F
Symbol
Parameter
Min
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock Frequency
Propagation Delay
CP to O
n
Output Enable Time
Output Disable Time
100
40
40
20
20
20
15
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
140
65
65
90
58
53
43
85
85
11 5
75
70
55
Max
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
60
40
40
20
20
20
15
10 5
11 0
14 0
10 0
80
75
Max
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
70
40
40
20
20
20
15
10 0
10 0
12 5
85
80
65
Max
MHz
ns
Units
ns
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup Time HIGH or LOW
D
n
to CP
Hold Time HIGH or LOW
D
n
to CP
CP Pulse Width
HIGH or LOW
20
20
20
20
70
60
Max
54F
T
A
V
CC
e
Mil
Min
25
20
20
25
70
60
Max
74F
T
A
V
CC
e
Com
Min
20
20
20
20
70
60
ns
Max
Units
ns
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
Temperature Range Family
74F
e
Commercial
54F
e
Military
Device Type
Package Code
P
e
Plastic DIP
D
e
Ceramic DIP
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
MSA
e
Shrink Small Outline (EIAJ SSOP)
374
S
C
X
Special Variations
QB
e
Military grade device with
environmental and burn-in
processing
X
e
Devices shipped in 13 reel
Temperature Range
C
e
Commercial (0 C to
a
70 C)
M
e
Military (
b
55 C to
a
125 C)
NOTE
Not required for MSA package code
4
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
5
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