Darlington current-sink outputs, with improved low-saturation
voltages
▪
CMOS, TTL compatible inputs
▪
Output transient protection
▪
Internal pull-down resistors
▪
Low-power CMOS latches
Description
The A6800 and A6801 latched-input BiMOS ICs merge
high-current, high-voltage outputs with CMOS logic. The
CMOS input section consists of 4 or 8 data (D type) latches
with associated common CLEAR, STROBE, and OUTPUT
ENABLE circuitry. The power outputs are bipolar NPN
Darlingtons. This merged technology provides versatile,
fl
exible interface. These BiMOS power interface ICs greatly
benefit the simplification of computer or microproces-
sor I/O. The A6800 ICs each contain four latched drivers.
A6801 ICs contain eight latched drivers.
The CMOS inputs are compatible with standard CMOS
circuits. TTL circuits may mandate the addition of input
pull-up resistors. The bipolar Darlington outputs are suitable
for directly driving many peripheral/power loads: relays,
lamps, solenoids, small DC motors, and so forth.
All devices have open-collector outputs and integral diodes
for inductive load transient suppression. The output transis-
tors are capable of sinking 600 mA and can withstand at
least 50 V in the off state. Because of limitations on package
power dissipation, the simultaneous operation of all driv-
ers at maximum rated current can only be accomplished
by a reduction in duty cycle. Outputs may be paralleled for
higher load current capability.
Continued on the next page…
Packages
A6800
14-pin 7.62 mm DIP
(A package)
A6800
14-pin SOICN
(L package)
A6801
22-pin 10.16 mm DIP
(A package)
A6801
24-pin SOICW
(LW package)
A6801
28-pin PLCC
(EP package)
Approximate scale 1:1
Functional Block Diagram
S UP P LY
V
DD
IN
N
OUT
N
C OMMON
S T R OB E
G R OUND
C LE AR
OUT P UT E NAB LE
T Y P IC AL MOS LAT C H
T Y P IC AL B IP OLAR DR IV E
C OMMON MOS C ONT R OL
26180.110e
A6800
and
A6801
DABiC-5 Latched Sink Drivers
Description (continued)
The A6800SA is furnished in a 14-pin DIP with 7.62 mm
(0.300 in.) row centers; the A6800SL and A6801SLW in surface-
mountable SOICs; the A6801SA in a 22-pin DIP with 10.16 mm
(0.400 in.) row centers; the A6801SEP in a 28-lead PLCC. These
devices are lead (Pb) free, with 100% matte tin plated leadframes.
Applications include:
▪
Relays
▪
Lamps
▪
Solenoids
▪
Small DC motors
Selection Guide
Part Number
A6800SA-T
A6800SL-T
A6800SLTR-T
A6801SA-T*
A6801SEP-T
A6801SEPTR-T
A6801SLW-T
A6801SLWTR-T
Package
14-pin DIP
14-pin SOIC
14-pin SOIC
22-pin DIP
28-pin PLCC
28-pin PLCC
24-pin SOIC
24-pin SOIC
Packing
25 per tube
56 per tube
2500 per reel
17 per tube
38 per tube
800 per reel
31 per tube
1000 per reel
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the
variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer appli-
cations. The variant should not be purchased for new design applications because of obsolescence in the near
future. Samples are no longer available. Status date change April 28, 2008. Deadline for receipt of LAST TIME
BUY orders is October 31, 2008.
Absolute Maximum Ratings*
Characteristic
Output Voltage
Supply Voltage
Input Voltage Range
Continuous Collector Current
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
Symbol
V
CE
V
DD
V
IN
I
C
T
A
T
J
(max)
T
stg
Range S
Notes
Rating
50
7
–0.3 to V
DD
+ 0.3
600
–20 to 85
150
–55 to 150
Units
V
V
V
mA
ºC
ºC
ºC
*Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to
extremely high static-electrical charges.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6800
and
A6801
DABiC-5 Latched Sink Drivers
Allowable Power Dissipation
2.5
22-P IN DIP , R
θ
JA
= 56°C /W
28-LE AD P LC C , R
θ
JA
= 68°C /W
14-P IN DIP , R
θ
JA
= 73°C /W
P A C K A G E P OWE R DIS S IP A T ION (W)
2.0
24-LE AD S OIC , R
θ
JA
= 85°C /W
1.5
1.0
0.5
14-LE AD S OIC , R
θ
JA
= 120°C /W
0
25
50
75
100
125
150
A MB IE NT T E MP E R A T UR E (º C )
Typical Input Circuit
V
DD
IN
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6800
and
A6801
DABiC-5 Latched Sink Drivers
ELECTRICAL CHARACTERISTICS
1
Unless otherwise noted: T
A
= 25°C, logic supply operating voltage V
DD
= 3.0 to 5.5 V
V
DD
= 3.3 V
Characteristic
Output Leakage Current
Output Sustaining Voltage
Collector-Emitter Saturation
Voltage
Input Voltage
Input Resistance
Logic Supply Current
Clamp Diode Leakage Current
Clamp Diode Forward Voltage
Output Fall Time
Output Rise Time
V
DD
= 5 V
Typ.
–
–
0.8
0.9
1.0
–
–
–
–
130
–
–
80
100
Symbol
I
CEX
V
CE(SUS)
V
CE(SAT)
V
IN(1)
V
IN(0)
R
IN
I
DD(1)
I
DD(0)
I
r
V
f
t
f
t
r
Test Conditions
V
OUT
= 50 V
I
OUT
= 350 mA, L = 3 mH
I
OUT
= 100 mA
I
OUT
= 200 mA
I
OUT
= 350 mA (See note 2)
Min.
–
35
–
–
–
2.2
–
50
Typ.
–
–
0.8
0.9
1.0
–
–
–
–
130
–
–
80
100
Max. Min.
10
–
1.0
1.1
1.3
–
1.1
–
1.0
150
50
2.0
–
–
–
35
–
–
–
3.3
–
50
–
–
–
–
–
–
Max.
10
–
1.0
1.1
1.3
–
1.7
–
1.0
150
50
2.0
–
–
Units
μA
V
V
V
V
V
V
kΩ
mA
μA
μA
V
ns
ns
One output on, I
OUT
= 100 mA
All outputs off
V
r
= 50 V
I
f
= 350 mA
V
CC
= 50 V, R1 = 500
Ω,
C1
≤
30 pF
V
CC
= 50 V, R1 = 500
Ω,
C1
≤
30 pF
–
–
–
–
–
–
1
2
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic 1.
Because of limitations on package power dissipation, the simultaneous operation of multiple drivers can only be accomplished by reduction in duty cycle.
Truth Table
OUT P UT
IN
N
0
1
X
X
X
X
S T R OB E
1
1
X
X
0
0
CLE AR
0
0
1
X
0
0
E NA B L E
0
0
X
1
0
0
t-1
X
X
X
X
ON
OF F
OUT
N
t
OF F
ON
OF F
OF F
ON
OF F
X = irrelevant
t-1 = previous output s tate
t = pres ent output s tate
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6800
and
A6801
DABiC-5 Latched Sink Drivers
Timing Requirements and Specifications
(Logic Levels are V
DD
and Ground)
CLEAR
G
STROBE
A
C
B
C
B
A
C
B
H
INN
D
OUTN
E
F
E
H
HIGH = ALL OUTPUTS DISABLED (OFF)
OUTPUT ENABLE
50%
t
en(BQ)
t
r
t
dis(BQ)
OUT
N
10%
t
f
DATA
90%
50%
Key
A
B
C
D
E
F
G
H
t
dis(BQ)
t
en(BQ)
Description
Minimum data active time before Strobe enabled (Data Set-Up Time)
Minimum data active time after Strobe disabled (Data Hold Time)
Minimum Strobe pulse width
Maximum time between Strobe activation and transition from output on to output off*
Maximum time between Strobe activation and transition from output off to output on*
Maximum time between Clear activation and transition from output on to output off*
Minimum Clear pulse width
Minimum data pulse width
Output Enable to output off delay*
Output Enable to output on delay*
Time (ns)
25
25
50
500
500
500
50
100
500
500
*Conditions for output transition testing are: V
CC
= 50 V, V
DD
= 5 V, R1 = 500
Ω,
C1
≤
30 pF.
NOTE: Information present at an input is transferred
to its latch when the STROBE is high. A high CLEAR
input will set all latches to the output off condition
regardless of the data or STROBE input levels. A high
OUTPUT ENABLE will set all outputs to the off con-
tdition, regardless of any other input conditions. When
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