A54SX32A-1FGG256A datasheet, PDF

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A54SX32A-1FGG256A: DescriptionField Programmable Gate Array, 2880 CLBs, 48000 Gates, 278MHz, 2880-Cell, CMOS, PBGA256, 1 MM, FBGA-256; CategoryProgrammable logic devices Programmable logic; File Size766KB，108 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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A54SX32A-1FGG256A Overview

Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 278MHz, 2880-Cell, CMOS, PBGA256, 1 MM, FBGA-256

A54SX32A-1FGG256A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
package instruction	LBGA, BGA256,16X16,40
Reach Compliance Code	compliant
Other features	32000 TYPICAL GATES AVAILABLE
maximum clock frequency	278 MHz
Combined latency of CLB-Max	1.1 ns
JESD-30 code	S-PBGA-B256
JESD-609 code	e1
length	17 mm
Humidity sensitivity level	3
Configurable number of logic blocks	2880
Equivalent number of gates	48000
Number of entries	203
Number of logical units	2880
Output times	203
Number of terminals	256
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	2880 CLBS, 48000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	2.5,2.5/5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.68 mm
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	17 mm
Base Number Matches	1

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v5.3

SX-A Family FPGAs

u e

™

Leading-Edge Performance

•

250 MHz System Performance

350 MHz Internal Performance

•

Specifications

•

12,000 to 108,000 Available System Gates

Up to 360 User-Programmable I/O Pins

Up to 2,012 Dedicated Flip-Flops

0.22

/ 0.25

CMOS Process Technology

Features

•

Hot-Swap Compliant I/Os

Power-Up/Down Friendly (No Sequencing Required

for Supply Voltages)

66 MHz PCI Compliant

Nonvolatile, Single-Chip Solution

Configurable I/O Support for 3.3 V / 5 V PCI, 5 V

TTL, 3.3 V LVTTL, 2.5 V LVCMOS2

2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with

5 V Input Tolerance and 5 V Drive Strength

Devices Support Multiple Temperature Grades

Configurable Weak-Resistor Pull-Up or Pull-Down

for I/O at Power-Up

Individual Output Slew Rate Control

Up to 100% Resource Utilization and 100% Pin

Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Boundary-Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

Actel Secure Programming Technology with

FuseLock™ Prevents Reverse Engineering and

Design Theft

Table 1 •

SX-A Product Profile

Device

Capacity

Typical Gates

System Gates

Logic Modules

Combinatorial Cells

Dedicated Flip-Flops

Maximum Flip-Flops

Maximum User I/Os

Global Clocks

Quadrant Clocks

Boundary Scan Testing

3.3 V / 5 V PCI

Input Set-Up (External)

Speed Grades

Temperature Grades

Package (by pin count)

PQFP

TQFP

PBGA

FBGA

CQFP

Notes:

1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers.

2. All –3 speed grades have been discontinued.

A54SX08A

8,000

12,000

768

512

256

512

130

Yes

0 ns

–F, Std, –1, –2

C, I, A, M

208

100, 144

–

144

–

A54SX16A

16,000

24,000

1,452

924

528

990

180

Yes

0 ns

–F, Std, –1, –2, –3

C, I, A, M

208

100, 144

–

144, 256

–

A54SX32A

32,000

48,000

2,880

1,800

1,080

1,980

249

Yes

0 ns

–F, Std, –1, –2, –3

C, I, A, M

208

100, 144, 176

329

144, 256, 484

208, 256

A54SX72A

72,000

108,000

6,036

4,024

2,012

4,024

360

Yes

0 ns

–F, Std, –1, –2, –3

C, I, A, M

208

–

256, 484

208, 256

February 2007

See the Actel website for the latest version of the datasheet.

SX-A Family FPGAs

Table of Contents

General Description

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

Detailed Specifications

Operating Conditions

Electrical Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Typical SX-A Standby Current

PCI Compliance for the SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Package Pin Assignments

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

329-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

International Traffic in Arms Regulations (ITAR) and Export Administration

Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

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