N25Q256A13E1241E datasheet, PDF

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N25Q256A13E1241E: DescriptionIC flash 256mbit 108mhz tbga; Categorystorage; File Size1MB，93 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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N25Q256A13E1241E Overview

IC flash 256mbit 108mhz tbga

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3V, 256Mb: Multiple I/O Serial Flash Memory

Features

Micron Serial NOR Flash Memory

3V, Multiple I/O, 4KB Sector Erase

N25Q256A

Features

•

SPI-compatible serial bus interface

Double transfer rate (DTR) mode

2.7–3.6V single supply voltage

108 MHz (MAX) clock frequency supported for all

protocols in single transfer rate (STR) mode

54 MHz (MAX) clock frequency supported for all

protocols in DTR mode

Dual/quad I/O instruction provides increased

throughput up to 54 MB/s

Supported protocols

– Extended SPI, dual I/O, and quad I/O

– DTR mode supported on all

Execute-in-place (XIP) mode for all three protocols

– Configurable via volatile or nonvolatile registers

– Enables memory to work in XIP mode directly af-

ter power-on

PROGRAM/ERASE SUSPEND operations

Continuous read of entire memory via a single com-

mand

– Fast read

– Quad or dual output fast read

– Quad or dual I/O fast read

Flexible to fit application

– Configurable number of dummy cycles

– Output buffer configurable

Software reset

3-byte and 4-byte addressability mode supported

64-byte, user-lockable, one-time programmable

(OTP) dedicated area

An additional reset pin is available on the following

devices

– N25Q256A83ESF40x, N25Q256A83E1240x,

N25Q256A83ESFA0F

Erase capability

– Subsector erase 4KB uniform granularity blocks

– Sector erase 64KB uniform granularity blocks

– Full-chip erase

• Write protection

– Software write protection applicable to every

64KB sector via volatile lock bit

– Hardware write protection: protected area size

defined by five nonvolatile bits (BP0, BP1, BP2,

BP3, and TB)

– Additional smart protections, available upon re-

quest

• Electronic signature

– JEDEC-standard 2-byte signature (BA19h)

– Unique ID of 17 read-only bytes including: addi-

tional extended device ID (EDID) to identify de-

vice factory options; customized factory data

• Minimum 100,000 ERASE cycles per sector

• More than 20 years data retention

• Packages JEDEC standard, all RoHS compliant

– V-PDFN-8/8mm x 6mm (also known as SON,

DFPN, MLP MLF)

– SOP2-16/300mils (also known as SO16W, SO16-

Wide, SOIC-16)

– T-PBGA-24b05/6mm x 8mm (also known as

TBGA24)

•

PDF: 09005aef84566603

n25q_256mb_65nm.pdf - Rev. T 03/14 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

3V, 256Mb: Multiple I/O Serial Flash Memory

Features

Contents

Device Description ........................................................................................................................................... 6

Features ....................................................................................................................................................... 6

3-Byte Address and 4-Byte Address Modes ..................................................................................................... 6

Operating Protocols ...................................................................................................................................... 6

XIP Mode ..................................................................................................................................................... 6

Device Configurability .................................................................................................................................. 7

Signal Assignments ........................................................................................................................................... 8

Signal Descriptions ......................................................................................................................................... 10

Memory Organization .................................................................................................................................... 12

Memory Configuration and Block Diagram .................................................................................................. 12

Memory Map – 256Mb Density ....................................................................................................................... 13

Device Protection ........................................................................................................................................... 14

Block Protection Areas ................................................................................................................................ 15

Serial Peripheral Interface Modes .................................................................................................................... 17

SPI Protocols .................................................................................................................................................. 19

Nonvolatile and Volatile Registers ................................................................................................................... 20

Status Register ............................................................................................................................................ 21

Nonvolatile and Volatile Configuration Registers .......................................................................................... 22

Extended Address Register .......................................................................................................................... 25

Enhanced Volatile Configuration Register .................................................................................................... 26

Flag Status Register ..................................................................................................................................... 26

Command Definitions .................................................................................................................................... 28

READ REGISTER and WRITE REGISTER Operations ........................................................................................ 32

READ STATUS REGISTER or FLAG STATUS REGISTER Command ................................................................ 32

READ NONVOLATILE CONFIGURATION REGISTER Command ................................................................... 32

READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command .................................. 33

READ EXTENDED ADDRESS REGISTER Command ..................................................................................... 33

WRITE STATUS REGISTER Command ......................................................................................................... 33

WRITE NONVOLATILE CONFIGURATION REGISTER Command ................................................................. 34

WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command ................................. 34

WRITE EXTENDED ADDRESS REGISTER Command ................................................................................... 35

READ LOCK REGISTER Command .............................................................................................................. 35

WRITE LOCK REGISTER Command ............................................................................................................ 36

CLEAR FLAG STATUS REGISTER Command ................................................................................................ 37

READ IDENTIFICATION Operations ............................................................................................................... 38

READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 38

READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 39

READ MEMORY Operations ............................................................................................................................ 43

3-Byte Address ........................................................................................................................................... 43

4-Byte Address ........................................................................................................................................... 45

READ MEMORY Operations Timing – Single Transfer Rate ........................................................................... 46

READ MEMORY Operations Timing – Double Transfer Rate ......................................................................... 50

PROGRAM Operations .................................................................................................................................... 54

WRITE Operations .......................................................................................................................................... 59

WRITE ENABLE Command ......................................................................................................................... 59

WRITE DISABLE Command ........................................................................................................................ 59

ERASE Operations .......................................................................................................................................... 61

SUBSECTOR ERASE Command ................................................................................................................... 61

SECTOR ERASE Command ......................................................................................................................... 61

BULK ERASE Command ............................................................................................................................. 62

PDF: 09005aef84566603

n25q_256mb_65nm.pdf - Rev. T 03/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

3V, 256Mb: Multiple I/O Serial Flash Memory

Features

PROGRAM/ERASE SUSPEND Command .....................................................................................................

PROGRAM/ERASE RESUME Command ......................................................................................................

RESET Operations ..........................................................................................................................................

RESET ENABLE and RESET MEMORY Command ........................................................................................

RESET Conditions ......................................................................................................................................

ONE TIME PROGRAMMABLE Operations .......................................................................................................

READ OTP ARRAY Command ......................................................................................................................

PROGRAM OTP ARRAY Command ..............................................................................................................

ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode .................................................................

ENTER or EXIT 4-BYTE ADDRESS MODE Command ...................................................................................

ENTER or EXIT QUAD Command ................................................................................................................

XIP Mode .......................................................................................................................................................

Activate or Terminate XIP Using Volatile Configuration Register ...................................................................

Activate or Terminate XIP Using Nonvolatile Configuration Register .............................................................

Confirmation Bit Settings Required to Activate or Terminate XIP ..................................................................

Terminating XIP After a Controller and Memory Reset .................................................................................

Power Up and Power Down .............................................................................................................................

Power Up and Power Down Requirements ...................................................................................................

Power Loss Recovery Sequence ...................................................................................................................

AC Reset Specifications ...................................................................................................................................

Absolute Ratings and Operating Conditions .....................................................................................................

DC Characteristics and Operating Conditions ..................................................................................................

AC Characteristics and Operating Conditions ..................................................................................................

Package Dimensions .......................................................................................................................................

Part Number Ordering Information .................................................................................................................

Revision History .............................................................................................................................................

Rev. T – 03/14 .............................................................................................................................................

Rev. S – 11/13 .............................................................................................................................................

Rev. R – 09/13 .............................................................................................................................................

Rev. Q – 05/13 .............................................................................................................................................

Rev. P – 01/13 .............................................................................................................................................

Rev. O – 12/12 .............................................................................................................................................

Rev. N – 11/12 .............................................................................................................................................

Rev. M – 09/12 ............................................................................................................................................

Rev. L – 08/12 .............................................................................................................................................

Rev. K – 07/12 .............................................................................................................................................

Rev. J – 06/12 ..............................................................................................................................................

Rev. I – 01/12 ..............................................................................................................................................

Rev. H – 11/11 .............................................................................................................................................

Rev. G – 07/11 .............................................................................................................................................

Rev. F – 07/11 .............................................................................................................................................

Rev. E – 05/11 .............................................................................................................................................

Rev. D – 05/11 .............................................................................................................................................

Rev. C – 11/10 .............................................................................................................................................

Rev. B – 08/10 .............................................................................................................................................

Rev. A – 06/10 .............................................................................................................................................

PDF: 09005aef84566603

n25q_256mb_65nm.pdf - Rev. T 03/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

3V, 256Mb: Multiple I/O Serial Flash Memory

Features

List of Figures

Figure 1: Logic Diagram ................................................................................................................................... 7

Figure 2: 8-Lead, VDFPN8 – MLP8 (Top View) .................................................................................................. 8

Figure 3: 16-Lead, Plastic Small Outline – SO16 (Top View) ............................................................................... 8

Figure 4: 24-Ball TBGA (Balls Down) ................................................................................................................ 9

Figure 5: Block Diagram ................................................................................................................................ 12

Figure 6: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18

Figure 7: SPI Modes ....................................................................................................................................... 18

Figure 8: Internal Configuration Register ........................................................................................................ 20

Figure 9: Upper and Lower 128Mb Memory Array Segments ........................................................................... 25

Figure 10: READ REGISTER Command .......................................................................................................... 32

Figure 11: WRITE REGISTER Command ......................................................................................................... 34

Figure 12: READ LOCK REGISTER Command ................................................................................................. 36

Figure 13: WRITE LOCK REGISTER Command ............................................................................................... 37

Figure 14: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 39

Figure 15: READ Command ........................................................................................................................... 46

Figure 16: FAST READ Command ................................................................................................................... 46

Figure 17: DUAL OUTPUT FAST READ Command – STR ................................................................................. 47

Figure 18: DUAL INPUT/OUTPUT FAST READ Command – STR ..................................................................... 47

Figure 19: QUAD OUTPUT FAST READ Command – STR ................................................................................ 48

Figure 20: QUAD INPUT/OUTPUT FAST READ Command – STR .................................................................... 48

Figure 21: FAST READ Command – DTR ......................................................................................................... 50

Figure 22: DUAL OUTPUT FAST READ Command – DTR ................................................................................ 51

Figure 23: DUAL INPUT/OUTPUT FAST READ Command – DTR .................................................................... 51

Figure 24: QUAD OUTPUT FAST READ Command – DTR ............................................................................... 52

Figure 25: QUAD INPUT/OUTPUT FAST READ Command – DTR ................................................................... 52

Figure 26: PAGE PROGRAM Command .......................................................................................................... 55

Figure 27: DUAL INPUT FAST PROGRAM Command ...................................................................................... 56

Figure 28: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 56

Figure 29: QUAD INPUT FAST PROGRAM Command ..................................................................................... 57

Figure 30: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 58

Figure 31: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 60

Figure 32: SUBSECTOR and SECTOR ERASE Command .................................................................................. 62

Figure 33: BULK ERASE Command ................................................................................................................ 63

Figure 34: RESET ENABLE and RESET MEMORY Command ........................................................................... 66

Figure 35: READ OTP Command .................................................................................................................... 67

Figure 36: PROGRAM OTP Command ............................................................................................................ 69

Figure 37: XIP Mode Directly After Power-On .................................................................................................. 72

Figure 38: Power-Up Timing .......................................................................................................................... 74

Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 77

Figure 40: Reset Enable ................................................................................................................................. 77

Figure 41: Serial Input Timing ........................................................................................................................ 77

Figure 42: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 78

Figure 43: Hold Timing .................................................................................................................................. 79

Figure 44: Output Timing .............................................................................................................................. 80

Figure 45: V

PPH

Timing .................................................................................................................................. 80

Figure 46: AC Timing Input/Output Reference Levels ...................................................................................... 82

Figure 47: V-PDFN-8/8mm x 6mm ................................................................................................................. 86

Figure 48: SOP2-16/300 mils .......................................................................................................................... 87

Figure 49: T-PBGA-24b05/6mm x 8mm .......................................................................................................... 88

PDF: 09005aef84566603

n25q_256mb_65nm.pdf - Rev. T 03/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

3V, 256Mb: Multiple I/O Serial Flash Memory

Features

List of Tables

Table 1: Signal Descriptions ...........................................................................................................................

Table 2: Sectors[511:0] ...................................................................................................................................

Table 3: Data Protection using Device Protocols .............................................................................................

Table 4: Memory Sector Protection Truth Table ..............................................................................................

Table 5: Protected Area Sizes – Upper Area .....................................................................................................

Table 6: Protected Area Sizes – Lower Area ......................................................................................................

Table 7: SPI Modes ........................................................................................................................................

Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................

Table 9: Status Register Bit Definitions ...........................................................................................................

Table 10: Nonvolatile Configuration Register Bit Definitions ...........................................................................

Table 11: Volatile Configuration Register Bit Definitions ..................................................................................

Table 12: Sequence of Bytes During Wrap .......................................................................................................

Table 13: Supported Clock Frequencies – STR .................................................................................................

Table 14: Supported Clock Frequencies – DTR ................................................................................................

Table 15: Extended Address Register Bit Definitions ........................................................................................

Table 16: Enhanced Volatile Configuration Register Bit Definitions ..................................................................

Table 17: Flag Status Register Bit Definitions ..................................................................................................

Table 18: Command Set .................................................................................................................................

Table 19: Lock Register ..................................................................................................................................

Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands .......................................

Table 21: Read ID Data Out ............................................................................................................................

Table 22: Extended Device ID, First Byte .........................................................................................................

Table 23: Serial Flash Discovery Parameter Data Structure ..............................................................................

Table 24: Parameter ID ..................................................................................................................................

Table 25: Command/Address/Data Lines for READ MEMORY Commands .......................................................

Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address .............................

Table 27: Data/Address Lines for PROGRAM Commands ................................................................................

Table 28: Suspend Parameters .......................................................................................................................

Table 29: Operations Allowed/Disallowed During Device States ......................................................................

Table 30: Reset Command Set ........................................................................................................................

Table 31: OTP Control Byte (Byte 64) ..............................................................................................................

Table 32: XIP Confirmation Bit .......................................................................................................................

Table 33: Effects of Running XIP in Different Protocols ....................................................................................

Table 34: Power-Up Timing and V

Threshold ...............................................................................................

Table 35: AC RESET Conditions ......................................................................................................................

Table 36: Absolute Ratings .............................................................................................................................

Table 37: Operating Conditions ......................................................................................................................

Table 38: Input/Output Capacitance ..............................................................................................................

Table 39: AC Timing Input/Output Conditions ...............................................................................................

Table 40: DC Current Characteristics and Operating Conditions ......................................................................

Table 41: DC Voltage Characteristics and Operating Conditions ......................................................................

Table 42: AC Characteristics and Operating Conditions ...................................................................................

Table 43: Part Number Information ................................................................................................................

Table 44: Package Details ...............................................................................................................................

PDF: 09005aef84566603

n25q_256mb_65nm.pdf - Rev. T 03/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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